BIT和ATE组合测试技术及其应用

详细介绍了BIT和ATE组合测试技术及其在机载电子设备测试与故障诊断的具体应用。应用表明BIT和ATE组合测试技术可有效提高设备的测试性。     

关于新一代航空电子设备ATE的初步设想

一、ATE技术的回顾与展望 ATE技术的发展始于五十年代。根据当时航空电子设备的情况,确立了飞行前测试、外场测试和中间车间测试的自动测试概念,建立了自动测试的一些基本原理。例如通过/不通过测试、故障隔离和预测、程序测试、自测试以及ATE标准化等概念。在第一代ATE的总体结构中,多采用穿孔纸带程序机构和硬件控制器。 数字计算机技术的发展,给ATE技术以极大的推动。键盘取代了操作员控制板,     

飞行管理计算机ATE综合测试系统设计

介绍了对飞行管理计算机进行自动测试的ATE8000系统。重点描述了系统的硬件组成及各部分功能、测试软件的组成、测试流程和实现方法。该系统较好地满足了测试手册的要求。     

通用无人机仿整机自动测试系统设计与实现

如何高效而精确的检测无人机机载设备的功能与性能,越来越重要且急迫。文章提出了一种将无人机机载计算机作为自动测试系统组成部分,并利用测试资源模拟无人机机载设备输入输出信号,仿真机载设备功能的测试系统设计方法,充分发挥机载计算机本身与其他机载设备的数据交联功能,以保持测试系统与实际装备工作环境一致,使得无人机整机BIT和正常工作过程能顺利完成。通过配备不同型号无人机的机载计算机和测试附件,可完成多型号无人机的测试,有效提高了内场检测维修的能力,提升了无人机的战斗力。     

民航航机电子附件维修检测通用自动测试设备（ATE）介绍

民用航空大部分的机载电子设备高度数字化、集成化，目前世界各发达国家均采用自动测试设备对这些设备进行功能测试。本文以AEROSPATLALE公司ATEC Series6通用型ATE为例，在硬件和软件平台两方面介绍了民用航空电子附件维修通用ATE的构成。     

基于虚拟仪器的机载模块性能测试系统

针对传统机载设备侧重于功能测试的技术缺陷,提出了一种机载模块性能测试系统。阐述了测试系统的架构设计和基于LabVIEW的算法实现,使用虚拟仪器技术,实现了航空电子总线ARINC429模块中信号性能的自动测试和故障报告。实验结果表明,该系统能有效完成模块信号性能的自动测试与故障报告,提高了航空电子自动测试设备的通用性与可靠性,对未来两级维修体制下的航空电子设备ATE的发展具有一定的现实意义。     

飞机灯光告警系统自动测试设备研制

告警控制盒是飞机灯光告警系统的核心部件,采集来自飞机各系统的告警信号,经分析处理后控制信号灯盒点亮、熄灭与闪烁来表达不同的告警信息。对告警控制盒进行了测试需求分析,基于ATE硬件平台设计了自动测试电路,采用了总线程控仪器和图形化测试软件等技术,实现了告警控制盒的功能和性能自动测试。经部队使用表明,该设备具有测试效率高、人机交互界面友好和操作简单等优点。     

ATE在航空电子部件检测中的应用

随着民用航空运输业的发展，大部分机载飞行控制设备（如飞行管理计算机、自动油门计算机等）高度数字化、集成化，已经不可能用人工手动对其进行测试检查，所以目前世界各发达国家的采用ATE（自动测试设备）完成此类工作。本文通过实例介绍了ATE对民用航空电子部件进行检测的一些实现方法。     

ATE综合校准系统的软件设计及实现

通用自动测试设备（ATE）的测量准确性、可靠性会直接影响飞机综合保障的质量,因此,对此检测设备进行全面有效的测试校准,是确保测试系统完成任务的关键。为了保障测试数据准确可靠和量值传递统一及实现现场的系统性校准工作,本课题以通用自动测试设备为对象,建立了一套基于虚拟仪器技术基础上的综合校准系统。本文对系统的软件结构设计进行了分析和设计,以LCOD原型生命周期为基础,使用了面对组件的设计模式,设计和实现了软件功能,使得该系统具有一定的兼容性和可移植性,并且为扩展留下了接口,同时保证了校准数据的可靠性和精确性。     

电路板测试技术进展

航空电子产品的测试以往经常采用生产线上的电路内测试(ICT)和对成品在自动测试设备(ATE)上的功能测试。80年代早期功能测试工具尚不普遍,其功能测试软件还很有限。功能测试的设计和编程是很费时的,往往产品已先出厂使用,而测试程序尚未完成。今天自动测试设备已较成熟,开发的功能测试程序已较多。印刷电路板(PCB)的测试利用钉床(bed of nail)夹具及各种相应的适配转换接口件实现电路内测试。然而由于电路板上密集度不断提高,ICT法已几乎难于实现。现将近年来测试方     

机内测试定量要求的现场试验验证方法研究

阐述了机内测试(BIT)定量要求现场试验验证方法的内涵和实施流程。根据置信度水平和功能单元覆盖要求计算BIT故障检测率、故障隔离率和虚警率综合验证的样本量,根据BIT参数的单侧置信限进行合格判断。给出了数据统计判据、分类流程和统一记录表格。通过案例应用说明了该方法的可行性。     

An Approach to Built-In Testing

The archiitecture and justification for an approach to built-in testing (BIT) in electronic circuits and systems is presented. The proposed system is capable of on-line fault detection and prediction up to the shop replaceable assembly (SRA) level and is designed to interface with external automatic test equipment (ATE) for off-line fault diagnosis within the SRA. The constituent parts of the BIT system have been extensively simulated and the approach appears to be suitable for hardware implementation both with respect to computational and economic considerations.     

Test results judgment method based on BIT faults

Built-in-test(BIT) is responsible for equipment fault detection, so the test data correctness directly influences diagnosis results. Equipment suffers all kinds of environment stresses, such as temperature, vibration, and electromagnetic stress. As embedded testing facility, BIT also suffers from these stresses and the interferences/faults are caused, so that the test course is influenced,resulting in incredible results. Therefore it is necessary to monitor test data and judge test failures.Stress monitor and BIT self-diagnosis would redound to BIT reliability, but the existing antijamming researches are mainly safeguard design and signal process. This paper focuses on test results monitor and BIT equipment(BITE) failure judge, and a series of improved approaches is proposed. Firstly the stress influences on components are illustrated and the effects on the diagnosis results are summarized. Secondly a composite BIT program is proposed with information integration, and a stress monitor program is given. Thirdly, based on the detailed analysis of system faults and forms of BIT results, the test sequence control method is proposed. It assists BITE failure judge and reduces error probability. Finally the validation cases prove that these approaches enhance credibility.     

面向FADEC系统BIT验证的综合故障注入器研究

为了评价航空发动机数字电子控制器机内自测试检测能力,提出了一种面向全权限数字电子控制(FADEC)系统机内自测试(BIT)验证的综合故障注入器的设计思想。综合故障注入器采用ARM处理器作为核心控制器;基于数模混合电路,分别通过后驱动技术和电压求和技术实现对数字电路节点和模拟电路节点的故障注入;针对各种传感器和执行机构的电气特征,设计了具有良好逼真度的接口模拟电路,从而与电子控制器(EEC)构成FADEC系统运行环境。通过对具有BIT功能的电子控制器原理样机的故障注入实验,证明该综合故障注入器作为航空发动机FADEC系统BIT设计和应用研究的工具是非常有效的。      

Evaluation of built-in test

Built-in test (BIT) provides fault finding as a means to aid in system assembly, test, and maintenance. An investigation to evaluate BIT of a particular electronics board used in the in-flight entertainment system for Boeing 777s is described. We found BIT proved useful when failure occurrences were uniquely associated with the operating environment, situations which can result in no-fault found, or could-not duplicate (CND) failures upon test. We also observed cases where the BIT failed to observe failures, and in some cases pointed to the wrong cause of failure. These and other advantages and disadvantages of BIT implementation are discussed     

机内测试虚警分析和控制

现代飞行器广泛采用机内测试(Built-intest,BIT)技术,以便对其内部故障进行自动检测、诊断和隔离,但是常规BIT面临诊断能力不足和诊断模糊性等问题,导致BIT虚警率高,难以有效发挥其应有的作用.本文论述了BIT虚警的基本理论、虚警的危害及现状,并从BIT虚警产生的原因分析入手,提出了解决虚警问题的一些方法和措施.     

Flyable fiber-optic radar target generator

Airborne radar relies on Built-in-Test (BIT) for fault detection, fault isolation and system calibration. The capability of BIT is often limited by space, weight, size and cost considerations. Furthermore, the radar does not have a test target that will allow BIT to perform in flight, closed-loop functional test of the complete radar system. This paper describes a fiber-optic based radar test target unit that provides a delayed replica of the transmitted radar signal. The unit will intercept a small amount of radar-transmitted energy, delay it in the fiber, then feed it back into the radar producing a calibrated “echo” at a predetermined radar range. The unit can be installed as part of the airborne radar. The details on the design and testing of a proof-of-concept unit are also given     

Role of BIT in support system maintenance and availability

The role of built in test (BIT) in electronic systems has grown in prominence with the advances in system complexity and concern over maintenance lifecycle costs of large systems. In an environment where standards drive system designs (and provide an avenue for focused advancement in technology), standards for BIT are very much in an evolutionary state. The reasons for advancing the effectiveness of BIT include reduced support overhead, greater, confidence in operation, and increased system availability. The cost of supporting military electronic systems (avionics, communications, and weapons systems) has driven much of the development in BIT technology. But what about the systems that support these end items that contain test and measurement instrumentation - such as automatic test equipment (ATE), simulators and avionics development suites? There has also been a beneficial effect on the maintenance and availability of these systems due to the infusion of BIT into their component assemblies. But the effect has been much more sporadic and fragmented. This paper looks at the state of BIT in test and measurement instruments, explain its affect on system readiness, and present ideas on how to improve BIT technologies and standards. This will not provide definitive answers to BIT development questions, since the factors that affect it are specific to the instrument itself. The topics covered in this paper are: definitions of built-in test, instrument BIT history, importance of BIT fault coverage and isolation in support systems, overview of BIT development process issues that limit the effectiveness of BIT Standards related to instrument BIT, making BIT more effective in support system maintenance and availability and conclusions.     

测试设备故障诊断专家系统的设计与实现

通过分析测试设备故障诊断专家系统的目的和任务,将模糊神经网络理论与专家系统结合后用于测试设备故障诊断,建立了故障诊断专家系统的模型。探讨了故障诊断专家系统中知识库的构建及维护、不精确推理等问题。用面向对象分析方法分析测试设备故障诊断专家系统,并用软件加以实现。