Role of BIT in support system maintenance and availability

The role of built in test (BIT) in electronic systems has grown in prominence with the advances in system complexity and concern over maintenance lifecycle costs of large systems. In an environment where standards drive system designs (and provide an avenue for focused advancement in technology), standards for BIT are very much in an evolutionary state. The reasons for advancing the effectiveness of BIT include reduced support overhead, greater, confidence in operation, and increased system availability. The cost of supporting military electronic systems (avionics, communications, and weapons systems) has driven much of the development in BIT technology. But what about the systems that support these end items that contain test and measurement instrumentation - such as automatic test equipment (ATE), simulators and avionics development suites? There has also been a beneficial effect on the maintenance and availability of these systems due to the infusion of BIT into their component assemblies. But the effect has been much more sporadic and fragmented. This paper looks at the state of BIT in test and measurement instruments, explain its affect on system readiness, and present ideas on how to improve BIT technologies and standards. This will not provide definitive answers to BIT development questions, since the factors that affect it are specific to the instrument itself. The topics covered in this paper are: definitions of built-in test, instrument BIT history, importance of BIT fault coverage and isolation in support systems, overview of BIT development process issues that limit the effectiveness of BIT Standards related to instrument BIT, making BIT more effective in support system maintenance and availability and conclusions.     

Test results judgment method based on BIT faults

Built-in-test(BIT) is responsible for equipment fault detection, so the test data correctness directly influences diagnosis results. Equipment suffers all kinds of environment stresses, such as temperature, vibration, and electromagnetic stress. As embedded testing facility, BIT also suffers from these stresses and the interferences/faults are caused, so that the test course is influenced,resulting in incredible results. Therefore it is necessary to monitor test data and judge test failures.Stress monitor and BIT self-diagnosis would redound to BIT reliability, but the existing antijamming researches are mainly safeguard design and signal process. This paper focuses on test results monitor and BIT equipment(BITE) failure judge, and a series of improved approaches is proposed. Firstly the stress influences on components are illustrated and the effects on the diagnosis results are summarized. Secondly a composite BIT program is proposed with information integration, and a stress monitor program is given. Thirdly, based on the detailed analysis of system faults and forms of BIT results, the test sequence control method is proposed. It assists BITE failure judge and reduces error probability. Finally the validation cases prove that these approaches enhance credibility.     

Evaluation of built-in test

Built-in test (BIT) provides fault finding as a means to aid in system assembly, test, and maintenance. An investigation to evaluate BIT of a particular electronics board used in the in-flight entertainment system for Boeing 777s is described. We found BIT proved useful when failure occurrences were uniquely associated with the operating environment, situations which can result in no-fault found, or could-not duplicate (CND) failures upon test. We also observed cases where the BIT failed to observe failures, and in some cases pointed to the wrong cause of failure. These and other advantages and disadvantages of BIT implementation are discussed     

飞行控制计算机模拟接口BIT电路设计及仿真

随着航空电子设备维修性要求的提高以及设备本身要求具备检测隔离故障的能力以缩短维修时间,机内测试(BIT)在测试领域研究中将越来越重要。功能电路BIT系统是航空电子设备整机BIT系统的重要组成部分,因此从解决实际问题出发,针对飞行控制计算机中的模拟输入和输出接口电路,提出了几种BIT的设计方法,并使用Multisim软件对所设计的BIT监测电路进行仿真,仿真结果表明,所设计的BIT电路是可靠及有效的。     

Using built-in-test to reduce TPS run times and improve TPSreliability

This paper addresses using information derived from Built-in-Test (BIT) to fault diagnose Units Under Test (UUTs), wherever possible. This philosophic approach to diagnostic testing is not new. It has been studied over the past 20 years under the visor of “Integrated Diagnostics”, but it has yet to be truly implemented in a “real life” military diagnostic test environment. The mindset of Test Program Set design engineering, along with customer and contractor management alike, remains “complete diagnostic testing based upon single catastrophic component failure modes”. If we are to generate cost efficient Test Program Sets (TPSs) under reduced military budget constraints, this will have to change! The test engineer must be encouraged to use methodologies to speed up development time and decrease TPS run times. Using present technology, this is possible now, and as the technology matures, will become a truly viable approach in the future. For the purpose of this paper, the author relies heavily on his extensive US Navy Automatic Test Equipment (ATE) and Test Program Set (TPS) experience, as well as on previous studies performed on using BIT to fault diagnose Unit Under Test failures on US Naval Air weapon systems     

基于ATE与BIT组合的NAMP自动测试与故障诊断系统设计

在对机械电气系统状态监控处理机(NAMP)功能、组成、BIT和ATE测试接口等进行测试需求分析基础上,基于ATE系统平台完成了NAMP的自动测试原理和测试流程设计,采用BIT和ATE组合测试技术完成了NAMP的自动测试,采用故障树法完成了NAMP的故障诊断功能。经故障注入实验和使用验证表明,该系统具有测试内容全面,故障定位准确,故障隔离率高等特点。     

基于通道校准和HMM的机载雷达健康状态评估

性能退化与间歇故障是机载雷达健康状态的重要反映。针对传统机载雷达健康评估方法缺乏整机级的监测指标、未能综合考虑性能退化和间歇故障，传统BIT电路难以监测间歇故障等工程难题，提出了基于通道校准链路，综合运用通道校准仿真技术、正态云、HMM建立起健康状态评估流程。首先，对通道误差与间歇故障进行分析，得到4类校正系数，建立误差与间歇故障注入仿真流程；然后，基于正态云，利用校正系数的样本方差来表征雷达系统的健康状态，提出统一健康模型，并给出HMM拓扑结构与参数设计方法；最后，建立起基于数据驱动的评估流程并开展应用研究。仿真实验验证了误差和间歇故障仿真流程的可行性、健康状态评估方法的有效性，可获得大于95%的评估准确率；应用案例表明所提方法可行，能解决工程上机载雷达健康状态评估的问题。     

An Approach to Built-In Testing

The archiitecture and justification for an approach to built-in testing (BIT) in electronic circuits and systems is presented. The proposed system is capable of on-line fault detection and prediction up to the shop replaceable assembly (SRA) level and is designed to interface with external automatic test equipment (ATE) for off-line fault diagnosis within the SRA. The constituent parts of the BIT system have been extensively simulated and the approach appears to be suitable for hardware implementation both with respect to computational and economic considerations.     

Smart BIT: a plan for intelligent built-in test

A major factor influencing the readiness of today's highly electronics-driven weapons systems is the amount of time spent maintaining them. The attainment of a better understanding of the causes for intermittent and other ill-defined failure modes and development of a greater appreciation for the effect of both external and internal environmental factors on the fault behavior of electronic systems will help to improve the BIT (built-in test) performance. Smart BIT is the name applied to a program of research and development sponsored by Rome Air Development Center (RADC) to investigate, develop, and apply artificial-intelligence (AI) techniques to effect BIT improvement. An overview of that program, its contents and purposes is provided. Deficiencies in current BIT implementations and potential benefits of the Smart BIT program are presented. Components of this approach are discussed and supporting technology areas highlighted. The current plan for implementing this approach is given along with a scenario describing its potential form     

航空发动机电子控制器可测试性技术应用研究

基于边界扫描的测试思想,提出了1种航空发动机电子控制器可测试性设计方案。通过器件管脚的边界扫描单元,在板级甚至多个目标板组成的复杂系统间,构建了1条在集成电路边界绕行的移位寄存器链,可以实现复杂集成电路的嵌入式测试。该方案还可以实现故障注入,对航空发动机电子控制器机内自测试(B IT)能力进行验证。     

BIT和ATE组合测试技术及其应用

详细介绍了BIT和ATE组合测试技术及其在机载电子设备测试与故障诊断的具体应用。应用表明BIT和ATE组合测试技术可有效提高设备的测试性。     

BIT综合表示模型研究

 在分析机内测试(BIT)主要设计要素组成的基础上,提出了BIT综合表示模型。建立了BIT综合表示模型的数学定义,包括BIT单元模型、BIT层次关系集合、BIT数据传送方式集合、BIT执行次序集合和BIT综合表示模型。在数学定义的基础上,进一步建立了BIT综合表示的框图模型和表格模型,这两种模型可以直接用于工程分析。最后,以某辅助导航系统为案例,进行了BIT综合表示模型的应用,给出了框图模型结果和表格模型结果,验证了该模型的可用性和有效性。     

机内测试定量要求的现场试验验证方法研究

阐述了机内测试(BIT)定量要求现场试验验证方法的内涵和实施流程。根据置信度水平和功能单元覆盖要求计算BIT故障检测率、故障隔离率和虚警率综合验证的样本量,根据BIT参数的单侧置信限进行合格判断。给出了数据统计判据、分类流程和统一记录表格。通过案例应用说明了该方法的可行性。     

机内测试虚警分析和控制

现代飞行器广泛采用机内测试(Built-intest,BIT)技术,以便对其内部故障进行自动检测、诊断和隔离,但是常规BIT面临诊断能力不足和诊断模糊性等问题,导致BIT虚警率高,难以有效发挥其应有的作用.本文论述了BIT虚警的基本理论、虚警的危害及现状,并从BIT虚警产生的原因分析入手,提出了解决虚警问题的一些方法和措施.     

面向FADEC系统BIT验证的综合故障注入器研究

为了评价航空发动机数字电子控制器机内自测试检测能力,提出了一种面向全权限数字电子控制(FADEC)系统机内自测试(BIT)验证的综合故障注入器的设计思想。综合故障注入器采用ARM处理器作为核心控制器;基于数模混合电路,分别通过后驱动技术和电压求和技术实现对数字电路节点和模拟电路节点的故障注入;针对各种传感器和执行机构的电气特征,设计了具有良好逼真度的接口模拟电路,从而与电子控制器(EEC)构成FADEC系统运行环境。通过对具有BIT功能的电子控制器原理样机的故障注入实验,证明该综合故障注入器作为航空发动机FADEC系统BIT设计和应用研究的工具是非常有效的。      

机载雷达BIT设计研究

首先分析了机载雷达自检测(BIT)采用的设计思想;然后论述了机载雷达自动实施的加电自检(PBIT)、连续自检(CBIT)、人工干预的中断自检(IBIT)和快速自检(QBIT);最后给出机载雷达BIT信息处理的流程.     

航空发动机电液伺服系统机载模型监控设计

为了监控航空发动机电液伺服系统中不易通过机内测试电路诊断的异常或故障,提出一种机载模型监控方法,采用AMESim工具进行系统的建模,之后对模型进行校准、实时化和线性化处理。在对监控算法进行了设计与仿真之后,用C代码编程实现了模型监控算法,并运行于发动机电子控制器中。对某发动机燃油计量装置的试验表明:机载模型监控可以有效监测系统中因元部件性能衰减、卡滞、零偏漂移等引起的异常或故障,并能补偿电液伺服阀的零偏漂移和容错运行,避免控制功能失效或过快降级。可为航空发动机及相关领域的电液伺服系统机载模型监控设计提供参考。     

基于时间应力分析的机内测试系统综合降虚警技术

 虚警率高是困扰机内测试（BIT）系统得到广泛应用的主要原因。针对该问题,从机电系统所承受时间应力的角度构建了机内测试系统综合降低虚警技术的总体模型。首先采用双支持向量机（SVM）的方法将实时应力信息与机内测试诊断结果相互关联。在此基础上,提出了基于核主元模糊聚类的虚警识别方法将机电系统多源信息进行综合分析,并通过优化决策实现多级降低机内测试系统虚警的目的。最后,针对某型直升机航空地平仪的机内测试系统进行了试验验证与分析。     

基于FTA的末制导雷达故障诊断专家系统研究

以某型末制导雷达为例,阐述了基于 FTA 技术的故障诊断专家系统的重要应用。文中首先论述了末制导雷达故障诊断专家系统的构成;其次论述了知识库的组成、故障树和规则的概念、推理机的工作原理,最后论述了系统的自学习机制。     

BIT技术在装备全寿命费用中影响分析

通过对BIT(Build in test,机内测试)技术在LCC(Life Cycle Costs,全寿命费用)中的影响分析,建立采用BIT技术后的LCC增量模型,研究了采用BIT技术对装备的全寿命费用产生的影响。同时基于国外现状,分析现今国内的情况,阐明采用BIT技术将在节约装备全寿命费用产生良性的影响。