嵌入式存储器自修复电路的设计与仿真

介绍了一种存储器自修复电路的仿真设计，其中内建自测试模块中的地址生成器采用LFSR设计，它面积开销相当小，从而大大降低了整个测试电路的硬件开销。而内建自修复模块采用基于一维冗余（冗余行块）结构的修复策略设计。通过16×32比特SRAM自修复电路设计实验验证了此方法的可行性。     

飞机全电刹车机电作动系统上电自检测

提出了一种飞机全电刹车机电作动（EMA）系统的上电自检测（POST）方法,以保证系统在运行前处于安全工作区域。通过检测,可及时准确地定位和更换故障部件,提高飞机出勤率。在系统运行之前,尽可能在有限的检测次数内全面准确地检测敏感元件,定位故障部件,避免造成刹车系统的二次伤害。针对逆变器和电机三相绕组组成的驱动回路,利用母线电容放电产生电流,完成检测。检测过程利用电容电压而非电源为逆变器供电,可防止过高的短路电流对电源的冲击,且电容上存储的能量有限,可有效避免短路故障对系统的二次伤害。检测方法在原有电路的基础上并未增加传感器和检测电路,但实现了逆变器功率管以及电机绕组,短路和开路故障的全面检测,且可定位出故障部件和故障原因。该机电作动系统上电自检测方法能够保证在一秒内完成系统全面自检测,经过1 000次正常及带故障试验,故障的误报率和漏报率保持在1‰以下。在现场试验中,系统可抵御飞机复杂的电磁环境（EME）,工作性能稳定。通过软件设置不同故障阈值,可方便移植到其他机电作动系统中。     

Design for testability for future digital avionics systems

The authors describe an integrated testing approach called the Maintenance and Diagnostic System (MADS), which was developed for digital avionics systems using VHSIC and semicustom devices. Mission/operational requirements dictate high availability with capability to detect 98% of all faults and isolate 90% of these faults to a line replacement module (LRM) or 95% of the faults to two LRMs. MADS achieves these goals by defining a module maintenance node (MMN) chip set for each LRM in the system and the design for testability concepts for hardware. The MMN aids parallel, high-speed testing of LRMs, isolating the fault(s) to a module/chip level while incurring less than 10% overhead. It uses the concepts of scan set design, pseudorandom test vector generation, output response compression, and separate scan set loops to test the SSI-MSI logic on the LRM. It also stores interim test results and run-time fault information to isolate the hard-to-reproduce failures and performs verification of interchip and intermodule wiring     

基于ATE与BIT组合的NAMP自动测试与故障诊断系统设计

在对机械电气系统状态监控处理机(NAMP)功能、组成、BIT和ATE测试接口等进行测试需求分析基础上,基于ATE系统平台完成了NAMP的自动测试原理和测试流程设计,采用BIT和ATE组合测试技术完成了NAMP的自动测试,采用故障树法完成了NAMP的故障诊断功能。经故障注入实验和使用验证表明,该系统具有测试内容全面,故障定位准确,故障隔离率高等特点。     

Software implemented transient fault detection in space computer

Computer systems operating in space environment are subject to different radiation phenomena, whose effects are often called “Soft Error”. Generally, these systems employ hardware techniques to address soft-errors, however, software techniques can provide a lower-cost and more flexible alternative. This paper presents a novel, software-only, transient-fault-detection technique, which is based on a new control flow checking scheme combined with software redundancy. The distinctive advantage of our approach over other fault tolerance techniques is the lower performance overhead with the higher fault coverage. It is able to cope with transient faults affecting data and the program control flow. By applying the proposed technique on several benchmark applications, we evaluate the error detection capabilities by means of several fault injection campaigns. Experimental results show that the proposed approach can detect more than 98% of the injected bit-flip faults with a mean execution time increase of 153%.     

Linux下无人机软件故障注入系统研究与设计

基于linux系统的软件故障注入方法,设计了一个软件故障注入系统UAVFI_L,采用硬件覆盖和故障模型的方法,模拟无人机系统的硬件故障,并着重讨论了在总线上注入故障的试验策略。最后用一台工控机和飞控计算机通讯,注入故障。故障注入试验结果表明了这种方案的正确性和可行性。     

双曲正切变换在VLSI设计中的研究应用

从双曲正切tanh变换在稳健的信号处理和统计估计的观点叙述了双曲正切变换的特性。介绍了利用双曲正切变换特性设计VLSI的方法。通过实际的设计证明,双曲正切变换特性在超大规模集成电路VLSI的设计中有着很好的应用前景。特别是在模拟VLSI的设计中,对包含噪声输入信号的估计和统计分析具有广泛的应用。     

边界扫描测试技术在集成电路测试中的应用

边界扫描技术是一种新型的VLSI电路测试及可测性设计方法,它提供了对电路板上元件的功能、互连及相互间影响进行测试的一种新方案。介绍了边界扫描技术的原理、结构,讨论了该技术在集成电路测试中的应用。     

Digital Computation Makes AFCS More Reliable

In airline service the reliability of a system is more than the confirmed failures for the system; it is the total removal experience of the system. Thus, the reliability of a system lies not only in the piece part failure rates, but also in the capability to verify and isolate failures. The application of digital technology brings several significant reliability improvements to automatic flight control systems (AFCS) when compared to contemporary analog systems. These advantages are demonstrated by the experience of the digital air data computer (DADC) of the DC-10 and the digital AFCS of the JA-37 Viggen. Experience with this equipment is reviewed, and the results are interpreted in terms of projections for airline DAFCS reliability. The digital system built-in test implemented by a stored program and the central processor gives a system integrity and dispatch reliability unequaled by analog systems. This high-integrity self-test reduces removal rates by giving line personnel a trustworthy tool and more complete automatic test processes for verifying maintenance actions. Digital circuit technology is directly suitable to largescale integrated circuits (LSIC) which reduce piece part counts and improve LRU reliability. Digital circuits are less subject to drift and the attendant difficulty to detect failures. These factors, coupled with the inherent high-integrity self-test, provide the basis for a significant improvement in reliability by the use of a digital automatic flight control system.     

Role of BIT in support system maintenance and availability

The role of built in test (BIT) in electronic systems has grown in prominence with the advances in system complexity and concern over maintenance lifecycle costs of large systems. In an environment where standards drive system designs (and provide an avenue for focused advancement in technology), standards for BIT are very much in an evolutionary state. The reasons for advancing the effectiveness of BIT include reduced support overhead, greater, confidence in operation, and increased system availability. The cost of supporting military electronic systems (avionics, communications, and weapons systems) has driven much of the development in BIT technology. But what about the systems that support these end items that contain test and measurement instrumentation - such as automatic test equipment (ATE), simulators and avionics development suites? There has also been a beneficial effect on the maintenance and availability of these systems due to the infusion of BIT into their component assemblies. But the effect has been much more sporadic and fragmented. This paper looks at the state of BIT in test and measurement instruments, explain its affect on system readiness, and present ideas on how to improve BIT technologies and standards. This will not provide definitive answers to BIT development questions, since the factors that affect it are specific to the instrument itself. The topics covered in this paper are: definitions of built-in test, instrument BIT history, importance of BIT fault coverage and isolation in support systems, overview of BIT development process issues that limit the effectiveness of BIT Standards related to instrument BIT, making BIT more effective in support system maintenance and availability and conclusions.     

A novel BIST scheme for circuit aging measurement of aerospace chips

The avionics working environment is bad, easy to accelerate aging of circuits. Circuit aging is one of the important factors that influence the reliability of avionics, so circuit aging testing is of great significance to improve the reliability of avionics. As continuing aging would degrade circuit performance, aging can be monitored through precise measurement of performance degradation. However, previous methods for predicting circuit performance have limited prediction accuracy. In this paper, we propose a novel Built-In Self-Test (BIST) scheme for circuit aging measurement, which constructs self-oscillation loops employing parts of critical paths and activates oscillations by specific test patterns. An aging signature counter is then used to capture the oscillation frequency and in turn measure the aging state of the circuit. We propose to implement this measurement process by BIST. Experimental results show that the proposed in-field aging measurement is robust with respect to process variations and can achieve a precision of about 90%. The application of this scheme has a certain value to improve the reliability of avionics systems.     

一种实用型报警装置的研制

本文综合地运用了５５５集成电路，ＴＷＨ９２４８，ＴＷＨ９２４９雷达式扫描探测传感集成电路的ＳＲ９Ｇ２６Ａ／Ｄ、Ｄ／Ａ转换语音存放电路等，中大规模集成电路。并利用一种简单的高频发射线路，而研制成的实用型报警装置。     

Fault self-repair strategy based on evolvable hardware and reparation balance technology

In the face of harsh natural environment applications such as earth-orbiting and deep space satellites, underwater sea vehicles, strong electromagnetic interference and temperature stress,the circuits faults appear easily. Circuit faults will inevitably lead to serious losses of availability or impeded mission success without self-repair over the mission duration. Traditional fault-repair methods based on redundant fault-tolerant technique are straightforward to implement, yet their area, power and weight cost can be excessive. Moreover they utilize all plug-in or component level circuits to realize redundant backup, such that their applicability is limited. Hence, a novel selfrepair technology based on evolvable hardware（EHW） and reparation balance technology（RBT） is proposed. Its cost is low, and fault self-repair of various circuits and devices can be realized through dynamic configuration. Making full use of the fault signals, correcting circuit can be found through EHW technique to realize the balance and compensation of the fault output-signals. In this paper, the self-repair model was analyzed which based on EHW and RBT technique, the specific self-repair strategy was studied, the corresponding self-repair circuit fault system was designed, and the typical faults were simulated and analyzed which combined with the actual electronic devices. Simulation results demonstrated that the proposed fault self-repair strategy was feasible. Compared to traditional techniques, fault self-repair based on EHW consumes fewer hardware resources, and the scope of fault self-repair was expanded significantly.     

Optimal weight extraction for adaptive beamforming using systolicarrays

Systolic algorithms and architectures for parallel and fully pipelined instantaneous optimal weight extraction for multiple sidelobe canceller (MSC) and minimum variance distortionless response (MVDR) beamformer are presented The proposed systolic parallelogram array processors are parallel and fully pipelined, and they can extract the optimal weights instantaneously without the need for forward or backward substitution. We also show that the square-root-free Givens method can be easily incorporated to improve the throughput rate and speed up the system. As a result these MSC and MVDR systolic array weight extraction system are suitable for real-time very large scale integration (VLSI) implementation in practical radar/sonar system     

液体火箭发动机启动过程实时在线故障检测算法

利用神经网络技术实现了液体火箭发动机启动过程的非线性辩识；提出并实现了一种基于辩识误差检验的故障检测策略。经大量实际发动机热试车数据验证表明，所提出的检测算法十分有效。由于算法所利用的监测参数均系实际发动机地面试车中所测量的参数，且检测算法在线工作时计算量十分小，因而所提出并实现的检测算法可以直接应用于工程实际。     

基于球体描述Vague决策的模拟电路故障诊断方法(英文)

提出一种基于球体描述Vague决策的模拟电路故障诊断方法。首先,采用小波变换预处理待测电路输出的电压故障特征。然后,每类样本集训练成一个最小超球体。最后,测试样本由本文定义的模糊决策规则进行判断,其中该规则由测试样本和描述球体中心之间的Vague加权距离得到。该模糊决策规则融合了测试样本正反隶属度值和描述球体的权值,可以有效地处理不确定信息。本文从理论上证明了该决策方法的可靠性。将该诊断方法应用于两种实际电路的测试,并与其他两种诊断方法进行对比。实验结果表明本文方法取得了良好的诊断性能,并减少诊断时间。     

VLSI architecture for SAR data compression

As a step towards a real-time signal aperture radar (SAR) correlator, custom very large scale integration (VLSI) architectures are developed. Considering the extremely short word length of the data, we derive three architectures with massive parallelism in bit space. Unlike frequency methods, no. degradation is introduced during convolution. Optimized for time and space, they are highly suited to VLSI implementation, and a small architecture with 80 taps operating at 10 MHz has been built using an FPGA     

发动机经验故障方程的建立与应用

本文提出了根据发动机故障样本建立故障方程的方法。发动机经验故障方程是不同于发动机小偏差方程的另一类故障方程,它为发动机故障诊断提供了一条简便易行的途径,并且使发动机故障诊断范围扩展到气路分析方法难以适用的场合。文中讨论了经验故障方程的建立方法及其在发动机故障诊断中的应用,给出了利用经验故障方程进行发动机故障诊断的实例。      

Knowledge Acquisition for ATE Diagnosis

An applied intelligence program for ATE fault diagnosis shows promise as an effective method to reduce mean time to repair (MTTR). The types of knowledge required by an intelligent diagnostic for VLSI test systems, the resources needed to derive that knowledge, the approach implemented to organize it, and the final form of the knowledge representations which resulted from our work are discussed in this paper.