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1.
A linear network of communicating processors is examined. The objective is to solve a computational problem in a minimal amount of time. The processors in the networks may be equipped either with or without front-end processors for communication off-loading. The cases of equal division of processing load and optimal division of processing load are discussed for both the network with front-end processors and the network without front end processors. An example of the inclusion of solution time, the time taken for processors to report the solution back to the problem originator, is also presented  相似文献   

2.
Tree networks of communicating processors are examined with the objective of solving a computational problem in a minimal amount of time. The processors in the networks may be equipped either with or without front-end processors for communicating of loading. The determination of the optimal division of processing load is discussed for the network with and the network without front-end processors. The inclusion of solution time, the time taken for sensors to report the solution back to originator, is discussed  相似文献   

3.
Ultimate performance limits to the aggregate processing speed of networks of processors that are processing a divisible job are described. These take the form of either closed-form expressions or numerical procedures to calculate the equivalent processing speed of an infinite number of processors. These processors are interconnected in either a linear daisy chain with load origination from the network interior or a tree topology. The tree topology is particularly general as a natural way to perform load distribution in a professor network topology with cycles (e.g., hypercube, toroidal network) is to use an embedded spanning tree. Such limits on performance are important as they provide an ideal baseline against which to compare the performance of finite configurations of processors.  相似文献   

4.
A tree network consisting of communicating processors is considered. The objective is to minimize the processing time by distributing the processing load to other nodes. The effect of the order of load distribution on the processing time is addressed. An algorithm which optimally determines the order of load distribution is developed. It is shown that the order depends only on the channel capacity between nodes but not on the computing capability of each node  相似文献   

5.
Optimal divisible job load sharing for bus networks   总被引:1,自引:0,他引:1  
Optimal load allocation for load sharing a divisible job over N processors interconnected in bus-oriented network is considered. The processors are equipped with front-end processors. It is analytically proved, for the first time, that a minimal solution time is achieved when the computation by each processor finishes at the same time. Closed form solutions for the minimum finish time and the optimal data allocation for each processor are also obtained  相似文献   

6.
The sensitivity to calibration and component errors of the receiver configurations used for monopulse processing of secondary surveillance radar (SSR) replies is analyzed. The effects of video gain error in amplitude processors and large Gaussian perturbations in phase processors are discussed. Phase processors are shown to be robust to variations in antenna difference pattern null depth. A half-angle phase processor that yields the benefits of phase processing without the sensitivity to system errors associated with conventional implementations is described  相似文献   

7.
The problem of optimally processing data with unknown focus is investigated. Optimum data processors are found by the method of maximum likelihood under a variety of assumptions that apply to most of the situations arising in practice. The unknown focus may be either an unknown parameter or an unknown random variable; the signal may be of known form or a random function; it is further assumed that the signal is received in additive, white, Gaussian noise. The problems of jointly estimating other unknown parameters and, in the case of a random signal, jointly estimating the signal, are also treated. The asymptotic variance and correlation of the estimators is discussed. Electrooptical realizations of the maximum likelihood computers are given. An iterative method of solution of the likelihood equation is also discussed. The discussion and results are directly applicable to the processing of synthetic aperture radar data.  相似文献   

8.
A linear daisy chain of processors in which processor load is divisible and shared among the processors is examined. It is shown that two or more processors can be collapsed into a single equivalent processor. This equivalence allows a characterization of the nature of the minimal time solution, a simple method to determine when to distribute load for linear daisy chain networks of processors without front end communication subprocessors and closed form expressions for the equivalent processing speed of infinitely large daisy chains of processors  相似文献   

9.
Some radar image processing algorithms such as shape-from-shading are particularly compute-intensive and time-consuming. If, in addition, a data set to be processed is large, then it may make sense to perform the processing of images on multiple workstations or parallel processing systems. We have implemented shape-from-shading, stereo matching, resampling, gridding, and visualization of terrain models in such a manner that they execute either on parallel machines or on clusters of workstations. We were motivated by the large image data set from NASA's Magellan mission to planet Venus, but received additional inspiration from the European Union's Center for Earth Observation program (CEO) and Austria's MISSION initiative for distributed processing of remote sensing images on remote workstations, using publicly-accessible algorithms. We developed a multi-processor approach that we denote as CDIP for Concurrent and Distributed Image Processing. The speedup for image processing tasks increases nearly linearly with the number of processors, be they on a parallel machine or arranged in a cluster of distributed workstations. Our approach adds benefits for users of complex image processing algorithms: the efforts for code porting and code maintenance are reduced and the necessity for specialized parallel processing hardware is eliminated.  相似文献   

10.
The goal of task allocation in a set of interconnected processors (computers) is to maximize the efficient use of resources and thus reduce the job turnaround time. Proposed is a simple yet effective method to allocate the tasks in multicomputer systems for minimizing the interprocessor communication cost subject to resource limitations defined by the system and designer. The limitations can be viewed as results from the load balancing since the execution time of each task, the number of available processors, processor speed, and memory capacity are known to the system or designer. As the number of processors increases, the probability of a failure existing somewhere in the systems at any time also increases. Very few established task allocation models have considered the reliability property. In multicomputer systems, we define system reliability as the probability that the system can run the tasks successfully. After the (nonredundant) task scheduling strategy is defined, tasks are then reallocated to processors statically and redundantly. This is a form of time redundancy, in which if some processors fail during the execution, all tasks can be completed on the remaining processors (but at a longer time). Due to static preallocation of tasks this method is simpler and thus more practical than well-known dynamic reconfiguration and rollback recovery techniques in multicomputer systems. We demonstrate the effectiveness of the task allocation and reallocation for hardware fault tolerance by illustrations of applying the methods to different examples and practical communications network multiprocessor system  相似文献   

11.
机载环境下数据处理规模的剧增以及人机混合智能的应用使得传统的以CPU 为核心计算单元的架构 已不能满足计算需求。在满足延时、精度等指标的情况下,选用高能效的处理器或处理器组合来快速准确地处 理这些数据成为机载计算领域面临的重要问题。按照常规处理器、领域专用加速器两大类型对各自主要代表性 处理器的架构特点进行了分析和总结,得出了各类处理器在机载情况下的主要适用场景和应用情况。根据领域 专用的设计思想开发了面向数据关联应用的专用加速器,对数据关联算法中的统计距离计算和分簇处理这两个 计算瓶颈进行了定制化的加速设计,并在基于FPGA 的平台上进行了测试验证,结果表明,加速器对于统计距 离计算的加速效果约为FT2000/4 单核性能的10 倍,对于分簇处理的加速效果约为FT2000/4 单核性能的3 倍, 整体运算速度相比FT2000/4 处理器的单核提升了5 倍。  相似文献   

12.
在使用多核处理器进行航空电子系统综合化设计时,各波形供应商通常因为各种限制,难以进行波形功能深度综合,因此目前的综合化仅仅是处理资源集中放置,并未很好地发挥多核处理器的效能。本文基于TI 公司多核DSP,设计了一种多波形管理框架,可以将多个无线电波形集中在一个多核DSP 中灵活部署、运行并管理,充分发挥多核处理器运算能力,提高系统资源利用率。  相似文献   

13.
Commercial standards adopted from the volume-driven electronics markets provide improved processing capacities over those widely used military standards and at reduced cost. Desired future capabilities and advanced functions, such as RPA, require the throughput, bandwidth, and memory provided by commercial processors and data buses. The primary issues needing resolution prior to implementation are related to operations in military rotorcraft environment, reliability, redundancy management, and fault and battle damage tolerance. In addition, some required network components presently do not exist in the preferred form factors. The ROSA project is providing effective laboratory demonstrations of COTS products and open systems specifications and standards to rotorcraft avionics. Preliminary cost estimates forecast large potential savings and create a compelling business case for follow-on research and transition to production systems. In addition, the project is developing a Rotorcraft Technical Architecture with the participation of many industry partners and will promote the resulting documentation as background materials for the JTA-A  相似文献   

14.
Scheduling a divisible load on a heterogeneous single-level tree network with processors having finite-size buffers is addressed. We first present the closed-form solutions for the case when the available buffer size at each site is assumed to be infinite. Then we analyze the case when these buffer sizes are of finite size. For the first time in the domain of DLT (divisible load theory) literature, the problem of scheduling with finite-size buffers is addressed. For this case, we present a novel algorithm, referred to as incremental balancing strategy, to obtain an optimal load distribution. Algorithm IBS adopts a strategy to feed the divisible load in a step-by-step incremental balancing fashion by taking advantage of the available closed-form solutions of the optimal scheduling for the case without buffer size constraints. Based on the rigorous mathematical analysis, a number of interesting and useful properties exhibited by the algorithm are proven. We present a very useful discussion on the implications of this problem on the effect of sequencing discussed in the literature. Also, the impact of Rule A, a rule that obtains a reduced optimal network to achieve optimal processing time by eliminating a redundant set of processor-link pairs, is also discussed. Numerical examples are presented.  相似文献   

15.
Optimization of a distributed detection network using theminimum global cost criterion results in local processors thatindividually form the likelihood ratio when the input observationvectors are statistically independent. In addition, the localthresholds and the network performance can be expressed as afunction of the receiver operating characteristics (ROCs) of the localprocessors. The performance of rive distributed networks arecompared numerically using local ROCs from the conic ROCfamily.  相似文献   

16.
A load sharing problem involving the optimal load allocation of divisible loads in a distributed computing system consisting of N processors interconnected through a bus-oriented network is investigated. For a divisible lend, the workload is infinitely divisible so that each fraction of the workload can be distributed and independently computed on each processor. For the first time in divisible load theory, an analysis is provided in the case when the processor speed and the channel speed are time varying due to background jobs submitted to the distributed system with nonnegligible communication delays. A numerical method to calculate the average of the time-varying processor speed and the channel speed and an algorithm to find the optimal allocation of the workload to minimize the total processing finish time are proposed via a deterministic analysis. A stochastic analysis which makes use of Markovian queueing theory is introduced for the case when arrival and departure times of the background jobs are not known  相似文献   

17.
《航空学报》1988,9(11):586-590
 一、引言 在中等脉冲重复频率(PRF)工作时,MTI-FFT-CFAR是PD或MTD雷达信号处理器的一种典型结构。Lawrence和Moore对MTD雷达在地杂波和气象杂波背景中的检测性能的计算中,假设了邻近距离单元中的杂波样本是独立同分布的(iid)。而在MTI-FFT-频域单元平均CFAR处理器中,频域单元的杂波样本明显偏离iid假设。门  相似文献   

18.
This paper deals with a new synthetic aperture radar (SAR) Processor based on a subspace detector designed for man-made target (MMT) detection. As MMTs are more accurately decribed by a set of canonical elements than with isotropic points, we develop a new algorithm which aims at using new models, instead of the isotropic point model commonly used in SAR processors. A subspace detector matched to canonical elements is included in the SAR processing. The implementation and the optimization of subspace detector SAR (SDSAR) algorithm is described. Simple examples of MMT detection in simulations and real data with a target hidden in a forest show the power of our approach. The SDSAR algorithm is shown to be the first robust and tractable algorithm relying on realistic scattering assumptions about the target.  相似文献   

19.
PARALLELCOMPUTATIONOFSUPER┐SONICBLUNTBODYVISCOUSFLOWFIELDSINPVMYangXiaohui,WangZhenghua,WangChengyao(Dept.1,NationalUniversit...  相似文献   

20.
A generic mission for an autonomous brilliant munition is presented and used to identify the functions that embedded signal processors must perform. Based on these functions and other operational factors such as weather, countermeasures, larger search areas, reduced false alarm rates, and increased munition maneuverability, the processing loads in bits/second messages/second, operations/second, and instructions/second are derived. An evaluation of general implementation issues such as the requirements for data fusion, distributed and parallel processing architectures, reliable software, and low-cost hardware is presented  相似文献   

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