Performance limits for processor networks with divisible jobs

Ultimate performance limits to the aggregate processing speed of networks of processors that are processing a divisible job are described. These take the form of either closed-form expressions or numerical procedures to calculate the equivalent processing speed of an infinite number of processors. These processors are interconnected in either a linear daisy chain with load origination from the network interior or a tree topology. The tree topology is particularly general as a natural way to perform load distribution in a professor network topology with cycles (e.g., hypercube, toroidal network) is to use an embedded spanning tree. Such limits on performance are important as they provide an ideal baseline against which to compare the performance of finite configurations of processors.     

Signature search time evaluation in flat file databases

For the first time, divisible load scheduling theory is used to solve for the expected time for searching for both single and multiple signatures in certain multiple processor database architectures. The target architectures examined for illustrative purposes are linear daisy chains and single level tree networks with single and multiple installment load distribution. The use of divisible load modeling and analysis yields elegant expressions for expected search time.     

Optimal divisible job load sharing for bus networks

Optimal load allocation for load sharing a divisible job over N processors interconnected in bus-oriented network is considered. The processors are equipped with front-end processors. It is analytically proved, for the first time, that a minimal solution time is achieved when the computation by each processor finishes at the same time. Closed form solutions for the minimum finish time and the optimal data allocation for each processor are also obtained     

Optimal time-varying load sharing for divisible loads

A load sharing problem involving the optimal load allocation of divisible loads in a distributed computing system consisting of N processors interconnected through a bus-oriented network is investigated. For a divisible lend, the workload is infinitely divisible so that each fraction of the workload can be distributed and independently computed on each processor. For the first time in divisible load theory, an analysis is provided in the case when the processor speed and the channel speed are time varying due to background jobs submitted to the distributed system with nonnegligible communication delays. A numerical method to calculate the average of the time-varying processor speed and the channel speed and an algorithm to find the optimal allocation of the workload to minimize the total processing finish time are proposed via a deterministic analysis. A stochastic analysis which makes use of Markovian queueing theory is introduced for the case when arrival and departure times of the background jobs are not known     

Distributed computation with communication delay [distributedintelligent sensor networks]

A linear network of communicating processors is examined. The objective is to solve a computational problem in a minimal amount of time. The processors in the networks may be equipped either with or without front-end processors for communication off-loading. The cases of equal division of processing load and optimal division of processing load are discussed for both the network with front-end processors and the network without front end processors. An example of the inclusion of solution time, the time taken for processors to report the solution back to the problem originator, is also presented     

Fast Algorithms for Time Domain Broadband Adaptive Array Processing

Recursive algorithms are presented for time domain, broadband, adaptive beamforming. The algorithms are rapidly converging and can be computationally efficient for a certain range of array processor parameters. The algorithms are presented for two forms of array processor. One form is a Frost-type structure in which explicit constraints are required for defining the array-look direction and also to control the sensitivity of the array processor to implementation errors. The other form is a partitioned array processor in which constraints are built into the processor and the adaptive weight control algorithm is therefore unconstrained. The two processors presented are both element-space processors but the algorithms can be applied also to beam-space processors.     

Task allocation and reallocation for fault tolerance inmulticomputer systems

The goal of task allocation in a set of interconnected processors (computers) is to maximize the efficient use of resources and thus reduce the job turnaround time. Proposed is a simple yet effective method to allocate the tasks in multicomputer systems for minimizing the interprocessor communication cost subject to resource limitations defined by the system and designer. The limitations can be viewed as results from the load balancing since the execution time of each task, the number of available processors, processor speed, and memory capacity are known to the system or designer. As the number of processors increases, the probability of a failure existing somewhere in the systems at any time also increases. Very few established task allocation models have considered the reliability property. In multicomputer systems, we define system reliability as the probability that the system can run the tasks successfully. After the (nonredundant) task scheduling strategy is defined, tasks are then reallocated to processors statically and redundantly. This is a form of time redundancy, in which if some processors fail during the execution, all tasks can be completed on the remaining processors (but at a longer time). Due to static preallocation of tasks this method is simpler and thus more practical than well-known dynamic reconfiguration and rollback recovery techniques in multicomputer systems. We demonstrate the effectiveness of the task allocation and reallocation for hardware fault tolerance by illustrations of applying the methods to different examples and practical communications network multiprocessor system     

Distributed computation in linear networks: closed-form solutions

A linear network of communicating processors is analyzed. The processors in the network may or may not be equipped with front-end processors. The processing load originates either at the boundary or at the interior of the network. Closed-form solutions and computational techniques are presented for the above situations, to obtain time optimal distribution of processing loads on the processors. Some important results are proved analytically using the closed-form expressions     

基于飞行器的飞行导航与飞行控制数据综合的研究

针对基于双处理器结构的飞控计算机数据综合过程中的时间同步、时间管理问题,采用了初始同步和周期同步相结合的方式,对任务运行中的误差进行了修正,并在时间同步的基础上,将控制链条分解成若干个控制单元进行分时调度,实现了双机并行处理.同时对数据综合过程中的数据处理方式也进行了讨论.     

多线程控制技术在面向对象实时仿真中的应用

随着实时仿真复杂性的提高,单个的处理器不足以完成所有的必需仿真计算任务。希望能在不同的处理器上完成实时仿真的不同任务,对称多处理器的机制需要软件支持,以使每个处理器通过共享内存进行信息交换。利用多线程控制技术,可以在非全进程开销或不使用共享内存的条件下,使用多处理器。其理由在于线程本身就蕴涵有共享地址的概念。一个多线程的实时程序,利用其中的主线程控制其它的辅助线程,每个处理器用于完成一个辅助的实时计算线程,主线程负责实时时钟的监控,当时钟到达时,启动相应的辅助线程,辅助线程利用图形用户界面(GUI)来监控仿真的进行。     

软件无线电的可重构流处理器体系结构

 针对软件无线电中存在通用数字信号处理器（DSP）计算能力不足以及专用基带处理器缺乏扩展性的问题,提出了一种新的处理器：面向软件无线电的可重构流处理器及相应的专用指令集。仿真证明,该处理器的可重构设计具备指令集扩展能力,可以对多种无线通信标准甚至是新的通信标准提供支持;面向软件无线电的流体系结构和专用指令集保证了对多种高速无线基带信号的实时处理,运算能力是通用DSP的5~13倍。该处理器为软件无线电中的硬件设计难题提供了一种新的解决途径。     

Analysis and design optimization of monopulse receivers forsecondary surveillance radar

The sensitivity to calibration and component errors of the receiver configurations used for monopulse processing of secondary surveillance radar (SSR) replies is analyzed. The effects of video gain error in amplitude processors and large Gaussian perturbations in phase processors are discussed. Phase processors are shown to be robust to variations in antenna difference pattern null depth. A half-angle phase processor that yields the benefits of phase processing without the sensitivity to system errors associated with conventional implementations is described     

Constrained Improvement MTI Radar Processors

A new class of staggered PRF MTI radar processors is developed in this paper. These processors are constrained to achieve a specified value of MTI improvement and, subject to this constraint, minimize variations in processor response as a function of target Doppler frequency. The selection of both filter weights and PRF stagger sequences is discussed and a number of representative designs are presented.     

多核操作系统自旋锁技术研究

多核操作系统通常采用自旋锁技术保证多核之间互斥.处理器核属于硬件设备,需要硬件锁机制实现核间互斥,各类处理器都提供相应的硬件指令实现自旋锁,如锁总线.处理器核在获取自旋不成功时,一直自旋,直到获取锁成功.自旋锁持有时间非常短,不引起睡眠,效率很高.     

A flexible processor for a digital adaptive array radar

A digital beamforming processor for an adaptive array radar is described. The functionality and the architecture of the processor are strongly driven by a goal of achieving adaptive null depths in the 60-dB to 70-dB range, which necessitates substantial preprocessing of each channel. In particular, conversion to baseband quadrature channels is accomplished digitally using a single A/D converter per channel, and FIR (finite impulse response) equalizing filters are employed in each channel to match channel transfer functions. The processor is highly modular, and this not only distributes the total processing load, but also the I/O (input/output) bandwidth requirement. This is accomplished by distributing the adaptive beamforming algorithm systolically across a linear array of processing nodes. The processor is expandable to a different number of channels and sufficiently flexible to be applied to other problems of an array signal processing nature. Experimental data presented demonstrate that the processor is capable of supporting channel-to-channel cancellation of interfering signals to the level of -65 dB     

Some Effects of Hard Limiting in Adaptive Antenna Systems

Adaptive antennas are often implemented with the Applebaum-Howells-type adaptive processor usually include a hard limiter between each antenna port and its correlation mixer, primarily for dynamic range compression. Brennan and Reed [3] analyzed the effects of hard limiting, and their conclusions suggest that it does not degrade the steady-state performance of the adaptive processor. Standard and hard-limited processors are compared and it is shown that when the two types of processor have the same sensitivity threshold, the hard-limited one can fail to provide sufficient interference cancellation when the correlation matrix of input signals has two or more eigenvalues of differing magnitudes. The consequence of hard limiting is that (depending on the processor design parameters) the larger of two or more signals can capture the hard limiter, allowing the smaller signals to pass through the processor essentially unattenuated. It is also shown that when a hard-limited processor is designed to provide the same cancellation as a standard one, it must have essentially as large a dynamic range as the standard, processor; therefore, it offers no advantage of dynamic range compression. Moreover, the hard-limited processor lacks a constant sensitivity threshold, which can be a desirable feature of a standard processor. Specific examples are presented for identical-element array antennas and for multiple-beam antennas.     

Distributed computation for a tree network with communicationdelays

Tree networks of communicating processors are examined with the objective of solving a computational problem in a minimal amount of time. The processors in the networks may be equipped either with or without front-end processors for communicating of loading. The determination of the optimal division of processing load is discussed for the network with and the network without front-end processors. The inclusion of solution time, the time taken for sensors to report the solution back to originator, is discussed     

Doppler Processor Rejection of Range Ambiguous Clutter

Doppler processors are used in radar to separate target returns from clutter. When the clutter is at a range farther than the unambiguous range of the radar, the ability to reject the clutter is degraded. In this article the degradation is analyzed for an N-pulse batch processor with Dolph weighting, and the results show how degradation varies with design sidelobe level.     

基于机载多核弱序存储模型的共享内存驱动软件设计方法研究

随着航空电子系统承载的应用日趋复杂，飞机对机载计算机的计算力和功耗比要求不断提升，这也推动了嵌入式多核处理器的加速应用和普及。多核处理器在航空电子设备的深入应用，随之而来的是运行其上的软件复杂度急剧上升，面向应用的航电系统设计面临挑战。多核处理器平台由于需要面对并行、指令乱序、资源共享冲突等问题，而目前国内大多数机载嵌入式软件和驱动仍然是基于单核处理器设计和实现的，影响最大的是在机载嵌入式实时操作系统环境下的驱动软件，因此需要充分考虑多核带来的各方面影响，尤其是需要兼顾共享内存等资源的使用冲突和实时高效要求。本文结合机载航电多核处理平台的特点，提出了一种基于机载多核弱序存储模型的共享内存驱动软件设计方法，并基于该方法设计了FC 总线驱动和MBI 总线驱动，项目应用结果表明，设计的驱动程序在多核处理器平台上数据传输正确，验证了方法的正确性和有效性。     

机载嵌入式系统中的多核处理架构研究与分析

与单核处理器相比较，多核处理器在性能、功耗、体积以及重量各方面都有绝对的优势，这使得多核处理器在机载嵌入式系统中的应用成为必然趋势。在分析了航空电子系统的任务特点之后，介绍了两种最常见的多核处理器系统架构：对称多处理（SMP）和非对称多处理（AMP），对这两种系统架构在机载嵌入式系统的应用进行了研究分析，并分析了其关键技术对实时性、安全性和确定性的影响。