基于改进型(14,8)循环码的SRAM型存储器多位翻转容错技术研究

SRAM型存储器空间应用通常采取纠一检二(SEC-DED)的方法,克服空间单粒子翻转(SEU)对其产生的影响。随着SRAM型存储器工艺尺寸的减小、核心电压的降低,空间高能粒子容易引起存储器单个基本字多位翻转(SWMU),导致SEC-DED防护方法失效。在研究辐射效应引起的SRAM型存储器多位翻转模式特点的基础上,提出一种基于改进型(14,8)循环码的系统级纠正一位随机错和两位、三位突发错同时检测随机两位错(SEC-DED-TAEC)的系统级容错方法。基于该方法的存储器系统容错设计具有实现简单、实时性高的特点,已成功应用于某型号空间自寻的信息处理系统。仿真试验及实际应用表明,该方法可以有效防护SRAM型存储器件SWMU错误,有效提高了空间信息处理系统可靠性,可以为其它空间电子系统设计提供参考。

Study of the Fault Tolerant Technology Based on (14,8)CRC Code for SRAM's SWMU

In space electronic system, the contents of SRAM are commonly protected by SEC-DED scheme. With the reduction of the feature size and the core power supply, the highly charged particles probably induce SWMU, leading to the failure of traditional SEC-DED scheme. Based on the physical signature for the SWMU of SRAM device, a modified (14, 8) systematic SEC-DED-TAEC code is proposed. The design based on this code can be easily implemented and has been applied in a space-borne integrated processor platform. The real-time performance of the proposed method and the high reliability of the space-borne integrated processor have been demonstrated by simulation and the application results. It can provide important reference for other space information processing systems.