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工作频率选择对GNSS接收机通道跟踪环路的影响CSCD
引用本文:王振伟,赵思浩,陆明泉.工作频率选择对GNSS接收机通道跟踪环路的影响CSCD[J].宇航计测技术,2015,35(1):28-33.
作者姓名:王振伟  赵思浩  陆明泉
作者单位:1、清华大学电子工程系,北京 100084
摘    要:GNSS接收机因须并行接收处理大量卫星信号,使用通道数量较多,功耗大是其主要难题,降低功耗的解决方法之一是让通道工作时钟采用较低的频率。通过分析工作时钟与所需处理的伪码频率的关系,本文给出了通道时钟频率对伪码相位分辨率和相位抖动幅度的影响。选取两种频率的工作时钟进行仿真实验,结果表明在相同仿真条件下,选用21MHz工作时钟与选用63MHz工作时钟相比,接收机的伪码测量精度、载波测量精度均下降1倍左右,但其引入的测量误差仍小于理论估算结果,选取较低的工作时钟频率是兼顾功耗与精度的折中方法,适合作为工程设计方案。

关 键 词:接收机  采样频率  相位抖动  延迟锁定环  GNSS  GNSS  receiver  Sampling  frequency  Phase  jitter  Delay  locked  loop

The Effect on Tracking Loop by Operating Frequency of GNSS Receiver Channel
WANG Zhen-wei,ZHAO Si-hao,LU Ming-quan.The Effect on Tracking Loop by Operating Frequency of GNSS Receiver Channel[J].Journal of Astronautic Metrology and Measurement,2015,35(1):28-33.
Authors:WANG Zhen-wei  ZHAO Si-hao  LU Ming-quan
Institution:1、Department of Electrical Engineering, Tsinghua University, Beijing 100084
Abstract:It is a major defect that the power consumption of GNSS receiver increases as parallel processing channels increases. One way of the solutions is to reduce operating frequency of the channel clock. By analyzing the relationship between the channel clock frequency and pseudo code frequency, it has been showed by this paper that the phase resolution and phase jitter of pseudo code will be affected by working clock. Selecting two working clock for simulation experiments, the results show that the pseudo-code measurement accuracy and the carrier measurement accuracy of the channel working with 21MHz clock is two times worse than that with 63MHz clock under the same simulation conditions; the error is still smaller than theoretically estimated results. Selecting a lower clock frequency is a compromise and suitable way to solve the contradiction between power consumption and measurement precision for a receiver as an engineering option.
Keywords:GNSS receiver                                                                                                                        Sampling frequency                                                                                                                        Phase jitter                                                                                                                        Delay locked loop
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