| 一种新型数字高精度伪码快速捕获延迟锁定环的设计与实现 |
| |
| 引用本文： | 张树勇,曹永刚,郭岩.一种新型数字高精度伪码快速捕获延迟锁定环的设计与实现[J].飞机设计,2007,27(5):76-80. |
| |
| 作者姓名： | 张树勇 曹永刚 郭岩 |
| |
| 作者单位： | 中国人民解放军驻沈阳飞机工业(集团)有限公司军事代表室,辽宁,沈阳,110034 |
| |
| 摘 要： | 介绍了一种新型全并行快速捕获延迟锁定环的设计与FPGA实现,捕获时间小于等于一个伪码周期,抗干扰容限大于80 dB。此快速捕获延迟锁定环实现127路全并行捕获和高精度跟踪,仅需存储130个PN码表,相对于其他并行捕获延迟锁定环或串并结合的环路,存储量约小2/3,并具有较高捕获精度。
|
| 关 键 词： | FPGA 伪码 捕获 跟踪 |
| 文章编号： | 1673-4599（2007）05-0076-05 |
| 收稿时间： | 2007-02-17 |
| 修稿时间： | 2007-07-13 |
Design and Implementation of a New Digital,High-Precision,Fast Pseudo-Code Capture and Delayed Locking Loop |
| |
| ZHANG Shu-yong,Cao Yong-gang,GUO Yan.Design and Implementation of a New Digital,High-Precision,Fast Pseudo-Code Capture and Delayed Locking Loop[J].Aircraft Design,2007,27(5):76-80. |
| |
| Authors: | ZHANG Shu-yong Cao Yong-gang GUO Yan |
| |
| Institution: | PLA Military Representative Office in Shenyang Aircraft Corporation, Shenyang 110034, China |
| |
| Abstract: | This paper describes the design and FPGA implementation of a new full parallel,fast capturing and delayed locking loop.The capture time is less than or equal to one pseudo-code period and the antijamming tolerance is larger than 80 dB.The fast capture and delayed locking loop achieves full parallel capture and the high accuracy tracking in 127 loops,and it is required only to memorize 130 PN code lists(that are approximately 1/3 of those for other parallel capture delayed locking loops or series-parallel loops),and provides higher capture accuracies than other loops. |
| |
| Keywords: | field-programmable gate arrays(FPGA) pseudo-code capture tracking |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
