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| 星上FPGA抗闩锁设计 | |
| 引用本文： | 杨雅,廖瑛,盖建宁,施敏华.星上FPGA抗闩锁设计[J].上海航天,2005,22(6):51-54. |
| 作者姓名： | 杨雅 廖瑛 盖建宁 施敏华 |
| 作者单位： | 1. 国防科学技术大学,航天与材料工程学院,湖南,长沙,410073;上海航天计算机研究所,上海,200050 2. 国防科学技术大学,航天与材料工程学院,湖南,长沙,410073 3. 上海航天计算机研究所,上海,200050 |
| 摘 要： | 根据星载电子设备CMOS电路中现场可编程逻辑阵列（FPGA）闩锁的发生机理，提出了输入／输出回路的抗锁定、二次屏蔽防止单粒子触发锁定等遏制闩锁触发条件，以及工作电源限流、闩锁检测与解除等遏制闩锁维持条件的设计，并给出了应用检测电路、板级锁定检测与解除、电流敏感器件检测电流和FPGA闩锁监测等应用实例。 |
| 关 键 词： | 星载电子设备 现场可编程逻辑阵列 抗闩锁 设计 可靠性 |
| 文章编号： | 1006-1630（2005）06-0051-04 |
| 收稿时间： | 2005-05-30 |
| 修稿时间： | 2005-07-22 |
Anti-Latch-Up Design of On-Board FPGA |
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| YANG Ya,LIAO Ying,GAI Jian-ning,SHI Min-hua.Anti-Latch-Up Design of On-Board FPGA[J].Aerospace Shanghai,2005,22(6):51-54. | |
| Authors: | YANG Ya LIAO Ying GAI Jian-ning SHI Min-hua |
| Institution: | 1. College of Aerospace and Material Engineering, NUDT, Changsha Hunan 410073, China; 2. Shanghai Aerospace Computer and Technology Institute, Shanghai 200050, China |
| Abstract: | According to the latch-up mechanism of field programmable gate array(FPGA) in CMOS circuit for on-board electronics,the designs for anti-latch-up triggering conditions such as anti-latch-up in input/output circuit and secondary shielding to prevent single event,anti-latch-up maintenance such as operation current limitation and latch-up detection and release were put forward in this paper.The application examples of employed test circuit,board latch-up detection and release,current detection by current sensor and FPGA latch-up monitoring were also given. |
| Keywords: | On-board embedded computer Field programmable gate array Anti-latch-up Design Reliability |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |