| 一种新型的嵌入式B时间码接口终端的设计 |
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| 引用本文： | 范一强,曹剑中,杨小军,刘波.一种新型的嵌入式B时间码接口终端的设计[J].航空计算技术,2005,35(1):89-92. |
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| 作者姓名： | 范一强 曹剑中 杨小军 刘波 |
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| 作者单位： | 1. 中国科学院,研究生院,北京100039;中国科学院,西安光学精密机械研究所,陕西,西安,710068
2. 中国科学院,西安光学精密机械研究所,陕西,西安,710068 |
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| 摘 要： | 在分析了B码码型特点及其接口终端基本工作原理的基础上,提出了一种新型的嵌入式B时间码接口终端的设计方法。该终端是由少量外围解调电路,一片复杂可编程逻辑阵列芯片和一片C805F系列单片机芯片组成的。对设计中存在的难点,如交流码的解调,同步脉冲信号的提取等部分,提出了较为新颖的解决方案。最后介绍了设计中使用的嵌入式芯片的性能特点。与传统的方法相比,该设计方案具有体积小,成本低,工作稳定等优点,完全能够替代传统的B码机箱的功能。
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| 关 键 词： | IRIG-B码 CPLD 硬件描述语言 Verilog VHDL |
| 文章编号： | 1671-654X(2005)01-0089-04 |
| 修稿时间： | 2004年12月23 |
A New Embedded Device Design for IRIG-B Code Time Unification |
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| FAN Yi-qiang,CAO Jian-zhong,YANG Xiao-jun,LIU Bo.A New Embedded Device Design for IRIG-B Code Time Unification[J].Aeronautical Computer Technique,2005,35(1):89-92. |
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| Authors: | FAN Yi-qiang CAO Jian-zhong YANG Xiao-jun LIU Bo |
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| Institution: | FAN Yi-qiang~ |
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| Abstract: | A new embedded device design for IRIG-B code time unification is given on the basis of analyzing wave characteristic of B-code and basic working principle of its interface terminal. This design is made up of demodulation circuit , a kind of complex programmable logical device and a kind of new-type single-chip microcomputer .The special stress is put on introducing some key technology ,such as drawing synchronous pulse and demodulating B(AC) code.The working performance of embedded chip in this design is introduced in detail .Compared with traditional methods , it has lots of advantages such as smaller size, lower costs and the more reliable stability . The experiment shows that main functions of traditional device can be realized successfully in this new design. |
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