基于冷备份多模冗余结构的BRAM自修复方法

随着现场可编程门阵列（FPGA）在空天电子系统中的广泛应用,受空间辐射恶劣环境影响,FPGA中重要的存储器电路BRAM,因采用SRAM技术极易发生位翻转故障,虽绝大部分情况表现为瞬时故障,但永久故障依然存在。针对BRAM自修复方法仅修复瞬时故障的现状,对能同时修复瞬时故障和永久故障的自修复方法进行研究,提出了一种冷备份多模冗余结构,用3个热备份模块和1个冷备份模块来构造BRAM,该结构可通过三模冗余刷新方法修复瞬时故障和冷备份替换方法修复永久故障。给出了整个BRAM自修复系统中各模块的电路结构和实现方法,实验验证了系统的自修复能力,并在可靠性、硬件资源和时间消耗3个方面,通过对比分析论证了自修复方法的有效性。     

胚胎电子细胞阵列中空闲细胞的配置

空闲细胞是胚胎电子细胞阵列(EECA)实现自修复的前提,空闲细胞越多,系统的可靠性越高,但过多的空闲细胞也将带来巨大的硬件资源消耗。在航空航天等领域,电子系统追求高可靠性的同时,硬件资源消耗也必须考虑,为优化胚胎电子细胞阵列中空闲细胞的配置,以阵列可靠性和硬件资源消耗为出发点,将多态系统理论引入到阵列的可靠性分析中,优化可靠性计算模型。针对经典胚胎电子细胞阵列,在不同自修复策略下,仿真并分析阵列的可靠性、硬件资源消耗与空闲细胞配置的关系。根据研究结果制定了不同自修复方式下空闲细胞的配置方法,同时兼顾可靠性和硬件资源消耗的要求。同时,研究了确定规模的胚胎电子细胞阵列自修复方式的选择方法。本文研究成果对推动胚胎电子细胞阵列的实际应用具有重要的意义。     

IMA平台重构中的人素和安全性研究

综合模块化航空电子(IMA)是一种建立在分布式计算环境之下的可以实现软硬件分离的架构,它可实现硬件模块应用的动态软件分配。即,IMA系统可以根据功能性和资源可用性来选择不同的配置。本文主要关注了IMA重构中涉及到的安全性及人素问题。解析了重构的过程以及人素与自动化方面的技术。事实证明,某些情况下安全有效的配置需要具备故障识别、安全要求、任务调度及资源分配限制以外的知识。并且平台的安全性设计还取决于人机系统是否实现了最佳结合。     

面向雷达天线平台的容错纠错策略及其FPGA实现

 针对雷达天线平台可能出现的传感器故障,提出了一种容错纠错策略。如果雷达天线平台周围的3条驱动腿中的某一个传感器发生故障,则可根据空间闭链机构约束,由其他正常工作驱动腿的传感器和中间从动腿的冗余传感器的测量值计算出故障传感器的应测值。推导了对应的位移传感器故障的容错重构算法,研究了基于现场可编程门阵列（FPGA）的上述容错策略的硬件实现方法。通过引入坐标旋转数字计算（CORDIC）算法使得FPGA运算中只需进行基本的移位和加/减操作;设计了基于FPGA的循环高速流水线处理器结构,使得重构算法的在线计算速度大大提高。仿真模拟了突变型传感器故障,结果表明,所提容错纠错方案能有效地保证雷达天线平台运行的安全性和可靠性。     

Fault self-repair strategy based on evolvable hardware and reparation balance technology

In the face of harsh natural environment applications such as earth-orbiting and deep space satellites, underwater sea vehicles, strong electromagnetic interference and temperature stress,the circuits faults appear easily. Circuit faults will inevitably lead to serious losses of availability or impeded mission success without self-repair over the mission duration. Traditional fault-repair methods based on redundant fault-tolerant technique are straightforward to implement, yet their area, power and weight cost can be excessive. Moreover they utilize all plug-in or component level circuits to realize redundant backup, such that their applicability is limited. Hence, a novel selfrepair technology based on evolvable hardware（EHW） and reparation balance technology（RBT） is proposed. Its cost is low, and fault self-repair of various circuits and devices can be realized through dynamic configuration. Making full use of the fault signals, correcting circuit can be found through EHW technique to realize the balance and compensation of the fault output-signals. In this paper, the self-repair model was analyzed which based on EHW and RBT technique, the specific self-repair strategy was studied, the corresponding self-repair circuit fault system was designed, and the typical faults were simulated and analyzed which combined with the actual electronic devices. Simulation results demonstrated that the proposed fault self-repair strategy was feasible. Compared to traditional techniques, fault self-repair based on EHW consumes fewer hardware resources, and the scope of fault self-repair was expanded significantly.     

应用设计过程的胚胎硬件细胞单元粒度优化方法

胚胎硬件的高可靠性主要由新颖的硬件体系和细胞电路结构来保障,缺乏应用设计过程的可靠性提高方法研究。分析了在应用设计过程中可调的胚胎硬件可靠性影响因素,针对细胞单元粒度不同会导致细胞面积变化从而影响细胞阵列可靠性的实际情况,对传统可靠性模型无法体现细胞面积变化的不足进行了改进,建立了新的可靠性模型。通过实例分析,总结出不同细胞单元粒度情况下的细胞阵列可靠性变化规律,进而给出细胞单元粒度优化选择方法,设计者基于该方法不需设计完整电路就能确定自身设计能力范围内获得最大可靠性的细胞单元粒度。     

Future architecture of flight control systems

The development of fault tolerant embedded control systems such as flight control systems (FCS) are currently highly specialized and time-consuming. We introduce a conceptual architecture for the next decade control system where all control and logic are distributed to a number of computer nodes locally linked to actuators and connected via a communication network. In this way, we substantially reduce the life-cycle cost of embedded systems and attain scalable fault tolerance. All fault tolerance is based on redundancy. Our philosophy is to cover permanent faults with hardware replication and handle all error processing caused by both permanent and transient faults with software techniques. With intelligent nodes and use of inherent redundancy we introduce a robust and simple fault tolerant system that utilizes minimum hardware and has bandwidth requirements of less than 300 kbits/s, which can be met with an electrical bus. The study is based on an FCS for JAS 39 Gripen, a multi-role combat aircraft that is statically unstable at subsonic speed.     

Optimal design of RTCs in digital circuit fault self-repair based on global signal optimization

Since digital circuits have been widely and thoroughly applied in various fields, electronic systems are increasingly more complicated and require greater reliability. Faults may occur in elec-tronic systems in complicated environments. If immediate field repairs are not made on the faults, elec-tronic systems will not run normally, and this will lead to serious losses. The traditional method for improving system reliability based on redundant fault-tolerant technique has been unable to meet the requirements. Therefore, on the basis of (evolvable hardware)-based and (reparation balance technology)-based electronic circuit fault self-repair strategy proposed in our preliminary work, the optimal design of rectification circuits (RTCs) in electronic circuit fault self-repair based on global sig-nal optimization is deeply researched in this paper. First of all, the basic theory of RTC optimal design based on global signal optimization is proposed. Secondly, relevant considerations and suitable ranges are analyzed. Then, the basic flow of RTC optimal design is researched. Eventually, a typical circuit is selected for simulation verification, and detailed simulated analysis is made on five circumstances that occur during RTC evolution. The simulation results prove that compared with the conventional design method based RTC, the global signal optimization design method based RTC is lower in hardware cost, faster in circuit evolution, higher in convergent precision, and higher in circuit evolution success rate. Therefore, the global signal optimization based RTC optimal design method applied in the elec-tronic circuit fault self-repair technology is proven to be feasible, effective, and advantageous.     

基于联合k/n(G)模型的DIMA系统可靠性建模与分析

针对分布式综合模块化航空电子（DIMA）系统的动态重构特性,分析了动态重构策略及重构过程,构建了面向DIMA系统的联合k/n（G）可靠性模型。以驻留于DIMA系统的综合显示功能为例进行了实验分析,讨论了系统重构过程可靠度与时间变化关系,给出了利用一般k/n（G）可靠性模型建模的可靠度变化曲线,通过对比分析验证了联合k/n（G）模型的适用性和合理性;通过参数敏感性分析,观察不同模块配置参数对系统可靠度的影响,得出相关结论,为提高DIMA系统动态重构过程的可靠性和优化资源配置提供指导。