Dynamics of the Phase-Locked Loop without a Limiter

The general (nth order) phase-locked loop is analyzed, of which the amplitude is not constant. The input carrier signal is amplitude-modulated by wide-band stationary Gaussian noise, and the signal, superposed with the additive white stationary Gaussian noise, enters the nonlimited phase-locked loop. Under the above assumptions the loop can be shown to constitute an n-dimensional vector Markov process, so that the process satisfies the n-dimensional Fokker-Plank equation. The probability density function depends on the effective loop signal-to-noise ratio and the effective modulation power.     

Coherent Square Wave Demodulation of Ideal Limiter Output

An ideal limiter may be used to single-bit quantize a noisy sinusoidal signal. This digitization is particularly economical if the signal is to be recorded. lt might then be desired to obtain phase coherence with the limited input signal. A single-bit digital phase-locked loop. utilizing a square wave reference, could be used for this purpose. The effects of coherent square wave demodulation on the signal-to-noise ratio and the (signal-to-noise spectral density) ratio are discussed. The latter result is directly applicable to the performance of the digital phase-locked loop.     

Optimum Strategies for Minimum Time Frequency Transitions in Phase-Locked Loops

Pontryagin's maximum principle is applied to minimize the time for a phase-locked loop to lock to a step change in frequency. In particular, a Type II phase-locked loop is considered in detail. Phase control and frequency control of the input signal are analyzed with the nonlinearity of the phase detector taken into consideration. It is shown that application of Pontryagin's maximum principle offers a decided advantage in shortening this time by proper control.     

Phase-Shift-Keyed Signal Detection with Noisy Reference Signals

This paper derives and graphically illustrates the performance characteristics of Phase-Shift-Keyed communication systems where the receiver's phase reference is noisy and derived from the observed waveform by means of a narrow-band tracking filter (a phase-locked loop). In particular, two phase measurement methods are considered. One method requires the transmission of an auxiliary carrier (in practice, this signal is usually referred to as the sync subcarrier). This carrier is tracked at the receiver by means of a phase-locked loop, and the output of this loop is used as a reference signal for performing a coherent detection. The second method is self-synchronizing in that the reference signal is derived from the modulated data signal by means of a squaring-loop. The statistics (and their properties) of the differenced-correlator outputs are derived and graphically illustrated as a function of the signal-to-noise ratio existing in the tracking filter's loop bandwidth and the signal-to-noise ratio in the data channel. Conclusions of these results as well as design trends are presented.     

S频段小数分频锁相环频率合成器实现与应用

传统的整数分频锁相环频率合成技术无法在单个环路实现高频率、低分辨率和低相噪的目标,小数分频锁相环在提高鉴相频率的同时减小分频计数值,从而降低相位噪声。针对USB统一测控系统的需要,本文提出基于单片小数分频锁相环的微波频率合成方法。实验结果表明,小数分频锁相环频率合成器具备良好的信号输出特性,可以为测控系统提供低成本频率合成方案。     

Switchless Control Strategies for Minimum Time Frequency Transitions in Phase-Locked Loops

The problem of minimum time frequency transitions in phase-locked loops with both phase and frequency controls applied is investigated using Pontryagin's maximum principle. Typically, a type II secondorder loop with a damping ratio of 0.707 subjected to a step change in the frequency of its input signal is considered and switchless control strategies that force the transients in the loop to settle down in minimum time are obtained.     

Interferences in Phase-Locked Loops

An analysis of the behavior of a second-order phase-locked loop is presented when an unwanted signal is added to the useful signal. Both signals are sinusoidal and unmodulated, and the analysis is made in the absence of additive noise. When the loop remains locked on the useful signal, a parasitic signal exists at the phase detector output. This signal produces a parasitic phase modulation of the VCO and a static phase error in the loop. The parasitic signal amplitude, the parasitic phase modulation index, and the static phase error are calculated. A necessary condition for the loop to remain in lock is derived. When the loop is initially unlocked, locking can occur either on the useful signal or on the unwanted signal, depending on the amplitude ratio and the frequency difference of the two signals. A formula allowing one to compute the pull-in time is obtained. When the loop locks on the useful signal, acquisition can be slower or faster than in the absence of an unwanted signal. The same phenomenon is observed when the loop locks on the unwanted signal.     

Effects of Automatic Gain Control on Phase-Locked Loop Behavior in the Presence of Interference

The behavior of a second-order phase-locked loop (PLL) in the presence of an interfering signal has been analyzed by different authors with different results. The discrepancy is attributed to the presence or absence of an automatic gain controlled amplifier preceeding the PLL. Simulation results verify that the presence of the automatic gain controlled amplifier reduces the tendency of the PLL to break lock from the desired signal in favor of the interfering signal     

FM Threshold Performance of the Frequency Demodulator with Feedback

The FM threshold performance of the frequency demodulator with feedback (FMFB) is experimentally optimized. Rules of thumb for the practical design of the FMFB with limiter in the loop are proposed. Such design rules provide for optimum FMFB threshold performance given specifications of the received signal. Equivalences among the FMFB, phase-locked loop, and limiter- discriminator offer some additional physical insight into the threshold-extending mechanism of the FMFB not presented by previous investigators.     

基于FPGA的北斗B1频点接收机 基带信号处理器设计

针对北斗二代B1频点信号比特翻转频繁的问题,设计并实现了基于FPGA的北斗B1频点导航接收机基带处理器.该处理器在信号捕获过程中设计了频率精细搜索的精捕获算法,避免了假捕获并且提高了捕获频率的精度;在载波跟踪环路中设计2阶锁频环辅助3阶锁相环的方案,以提高环路跟踪的动态性能.其中,锁频环和锁相环均设计了对比特翻转敏感的鉴别器,保证环路跟踪的准确性.试验结果表明,该基带处理器设计具有较高精度的捕获频率和良好的高动态跟踪能力.     

Improved Phase-Locked Loop Performance with Adaptive Phase Comparators

A major problem in phase-locked loop (PLL) design is to meet the requirements of both fast signal acquisition and good synchronous mode performance. This relation is reviewed for different types of phase comparators. As a result a new phase-and-frequency comparator is proposed. This comparator is based on an up-down counter principle and can be considered as an adaptive acquisition control circuit. The analysis of a PLL with the proposed phase comparator is based on an exact calculation method for the pull-in time. It is shown that fast signal acquisition is possible without affecting the filtering properties of the loop. Experimental results are given of the acquisition behavior of a second-order type-2 loop which show a good correspondence with the theoretical analysis.     

Phase-Lock Loop Jump Phenomenon in the Presence of Two Signals

Jump phenomena are known to exist in many non-linear systems [I], [2], [3]. The non-linear analysis presented in this paper explains and predicts the conditions for the jump phenomenon that is observed in a phase-locked loop (PLL) preceded by an automatic gain control (AGC). The jump phenomenon occurs when the frequency separation AM of two sinusoids at the input to the AGC is greater than the bandwidth B of the linearized PLL. If the loop is initially locked to the stronger signal, the weaker signal will frequency-modulate the PLL voltage-controlled oscillator (VCO) with a modulation frequency AI. The amplitude S2 of the weaker signal al can be increased until it becomes greater than the amplitude Si of the signal being tracked, without causing the loop to lose lock; i. e., the VCO continues to track the original signal. However, if the ratio of the amplitudes S2 S1 = R is increased above some critical value RC > 1, the loop will lose lock on the original signal, and jump to track the interfering signal. If the frequency separation is at least twice the PLL bandwidth, a good approximation for this critical ratio is Rc ? ?w/B.     

Frequency Tracking Characteristics of Split-Loop Phase-Locked Receivers

The excess time delay introduced by the incorporation of the intermediate frequency (IF) stage within the phase-locked loop (PLL) causes serious deterioration in the acquisition and tracking performance of the loop. The split-loop phase-locked system suggested by McGeehan and Sladen considerably reduces the effect of time delay on the acquisition and tracking performance of the loop. The frequency acquisition characteristics of the split-loop phase-locked receiver is investigated, and the effect of possible asymmetry in the arms of the loop on the acquisition range is examined. Closed-form approximate formulas are derived, and a comparison between split-, long-, and short-loop acquisition performance is presented.     

Optimum Acquisition of the Idling First-Order Phase-Locked Loop

Acquisition of the idling first-order phase-locked loop (PLL) is investigated. An analytical solution for the Fokker-Planck equation is found if the noise term is neglected. Furthermore, the modulation signal that optimizes the acquisition is obtained by use of phase-plane techniques and Pontryagin's minimum principle.     

Phase-Locked Loop Behavior near Threshold

The phase-locked loop behavior is analyzed following the quasilinearization Booton's method. When the loop is locked on an unmodulated input signal with a static phase error, the phase detector nonlinearity produces an interaction between the static phase error and the voltage-controlled-oscillator (VCO) noise phase fluctuations. Formulas allowing one to compute the static phase error increase and the VCO phase variance increase are derived. When the input signal is phase modulated, there is an interaction between the static phase error, the VCO noise phase fluctuations, and the input signal phase modulation. Formulas are obtained that allow one to compute the loop loss of performances (static phase error increase and VCO phase variance increase) and the coherent phase demodulator output signal-to-noise ratio decrease. Finally, a slight modification to Booton's procedure is proposed, leading to results in better agreement with experimental data.     

Comments on ?M-Ary Cpsk Detection with Noisy Reference and Interiverers?

The effect of cycle slips of the carrier recovery phase-locked loop (PLL) on the performance of coherent M-ary phase-shift keyed (MPSK) systems is dealt with. It is shown that each cycle slip causes a 1 bit error in a differentially encoded and Gray encoded signal stream. Different situations are investigated and compared with regard to the effect of these errors.     

An Optimum Phase Synchronizer in a Partially Coherent Receiver

The derivation and the statistical properties of the maximum a posteriori probability phase estimator of a sinusoidal signal in white Gaussian noise are considered. The probability density function of the phase estimate is developed. The estimator efficiency and performance as a phase synchronizer in a partially coherent receiver are calculated and compared with a first-order phase-locked loop phase estimator.     

Noise Performance of a Gated Phase-Locked Loop

The objectives of this paper are two. The first is to show that a gated phase-locked loop (GPLL) is a tracking device whose operation approximates that of a maximum likelihood estimator of the phase of a pulsed sinusoid imbedded in noise. The second is to determine the behavior of theb loop in the presence of noise. It is found that the loop performance is equivalent to that of a continuous phase-locked loop driven by the same noise, plus a continuous sinusoid which has the same power as the pulsed sinusoid at the input of the GPLL.     

On the Acquisition Time for an Apollo Ranging Code

An Apollo ranging system is considered whose phase reference is obtained by a phase-locked loop for bit synchronization. The bit phase reference is noisy, and the error probability for the ranging code is shown to depend on the input signal energy per bit to noise density ratio. The procedure of computing the acquisition time for the ranging code is then presented and the acquisition time for a lunar ranging code is plotted versus the input signal-to-noise density ratio.     

一种用于深空测距的数字化锁相环设计

在深空测距中，扩大锁相环捕获范围与提高锁相环对微弱信号检测能力是一对矛盾。为解决这一矛盾，本文提出一种基于频率引导与二次混频的数字化锁相环结构，并对其性能进行理论分析和计算机仿真。仿真结果表明，该锁相环可以很好地在较大范围内实现对微弱测距信号的捕获锁定。该结构已在实际测距接收机中使用。