支持多核的嵌入式操作系统关键技术研究

以分析当前支持多核的操作系统需实现的关键技术为基础,从多核操作系统的引导和初始化、多核操作系统任务管理、多核中断、核间通信以及核间同步与互斥等方面具体分析、研究支持多核的嵌入式操作系统的实现机制,提出了一种多核领域操作系统关键技术的解决思路.     

基于分区代理机制的FC通信虚拟化方案设计

随着航电系统的发展,处理平台的集成度逐步提高,多核处理器集成多个应用将是未来应用的趋势。 但在使用多核处理器的系统中,由于多个处理器核并行运行,需要解决通信资源在多个处理器核之间的共享问 题。本文提出了一种基于分区代理机制的FC 通信虚拟化方案设计,可以实现多核架构下多应用、多分区共享 FC 网络接口设备进行通信。     

基于多分区操作系统的多核确定性调度方法设计

为提高多分区操作系统环境下多核处理器的应用带来的操作系统任务调度的确定性,研究了多分环境下多核操作系统结构,从处理器核心和分区的资源分配和分区调度表的时间同步角度出发,采用了静态配置、处理器绑定和时间窗口调度方法,实现了处理器资源的确定性分配,解决了调度表之间的时间同步问题。测试结果表明,方法有效提高了分区环境下多核操作系统任务调度的确定性。     

IP over CCSDS协议适配的高速并行实现技术

天地一体化组网应用须在空间网和地面网之间部署IP over CCSDS(基于CCSDS空间链路承载IP业务)协议适配网关,以实现在高速CCSDS(空间数据系统咨询委员会)空间链路之上传输IP(互联网协议)数据包。针对此需求,提出一种IP over CCSDS协议适配的高速并行实现方法,并在Linux内核中采用多线程技术实现IP over CCSDS协议适配过程,通过实验进行测试与验证。测试表明,在处理器多核数目的范围内,协议适配处理性能随线程并发数目的增加而增加;当线程数目超过处理器核数时,受限于处理器核数和线程调度开销的影响,协议适配的性能并不能随着线程数目的增多而线性增加。后续,可利用FPGA(现场可编程门阵列)硬件逻辑电路的并行能力在硬件上实现协议适配的高速并行处理,并设计更高速率的同步接口,以从硬件上实现几千兆比特甚至几十千兆比特的高速IP over CCSDS协议适配。     

基于对称多处理架构的软件调试技术研究和实现

为了满足计算机领域用户对高性能及低功耗的双重需求,在深入研究多核现状的基础上,结合核间中断技术,提出了一种对称多处理架构下的软件调试器设计和实现方案。方案不仅成本低,而且不需要特殊调试硬件的支持,可为多核系统的故障诊断和分析提供参考借鉴。     

多核DSP实时图像处理平台设计与实现

为了实现对高帧率、高分辨率图像的智能化实时处理,要求图像处理系统具有较高的数据传输带宽和数据处理能力。采用多核DSP作为核心处理器来解决目前图像采集平台面临的数据传输瓶颈和处理瓶颈,利用FPGA硬件化并行处理的特性完成多路视频的预处理,设计了高速串口RapidIo通信接口实现视频的实时传输,对DSP的多核调度特性进行分析,保证处理的实时性,并采用相关算法验证系统的性能。     

基于机载多核弱序存储模型的共享内存驱动软件设计方法研究

随着航空电子系统承载的应用日趋复杂，飞机对机载计算机的计算力和功耗比要求不断提升，这也推动了嵌入式多核处理器的加速应用和普及。多核处理器在航空电子设备的深入应用，随之而来的是运行其上的软件复杂度急剧上升，面向应用的航电系统设计面临挑战。多核处理器平台由于需要面对并行、指令乱序、资源共享冲突等问题，而目前国内大多数机载嵌入式软件和驱动仍然是基于单核处理器设计和实现的，影响最大的是在机载嵌入式实时操作系统环境下的驱动软件，因此需要充分考虑多核带来的各方面影响，尤其是需要兼顾共享内存等资源的使用冲突和实时高效要求。本文结合机载航电多核处理平台的特点，提出了一种基于机载多核弱序存储模型的共享内存驱动软件设计方法，并基于该方法设计了FC 总线驱动和MBI 总线驱动，项目应用结果表明，设计的驱动程序在多核处理器平台上数据传输正确，验证了方法的正确性和有效性。     

基于多核DSP的多波形管理设计

在使用多核处理器进行航空电子系统综合化设计时,各波形供应商通常因为各种限制,难以进行波形功能深度综合,因此目前的综合化仅仅是处理资源集中放置,并未很好地发挥多核处理器的效能。本文基于TI 公司多核DSP,设计了一种多波形管理框架,可以将多个无线电波形集中在一个多核DSP 中灵活部署、运行并管理,充分发挥多核处理器运算能力,提高系统资源利用率。     

可重构芯片体系结构及其发展趋势

可重构芯片同时兼具通用处理器的灵活性和专用处理器的高效性,还具有高可靠性、低能耗、低成本等优点,在半导体产品中逐渐兴起。介绍了目前的一些典型可重构芯片的体系结构,从功能重构实现方式和可重构硬件类型角度分析了可重构芯片的体系结构,探讨了可重构芯片多核异构和可演化的发展趋势。     

机载嵌入式系统中的多核处理架构研究与分析

与单核处理器相比较，多核处理器在性能、功耗、体积以及重量各方面都有绝对的优势，这使得多核处理器在机载嵌入式系统中的应用成为必然趋势。在分析了航空电子系统的任务特点之后，介绍了两种最常见的多核处理器系统架构：对称多处理（SMP）和非对称多处理（AMP），对这两种系统架构在机载嵌入式系统的应用进行了研究分析，并分析了其关键技术对实时性、安全性和确定性的影响。     

机载通信管理器的处理器模块设计

MPC8245主要集成了PowerPC603e低功耗处理器核与PCI桥接器,以PCI同步总线作为局部总线,适合扩展为系统主控制器(同样也作为系统显示与通信的主控制器)。PCI同步总线最大传输率132 MB,完全满足管理器显示数据传输的基本要求。同时处理器器件集成了PIC控制器DMA控制器DUART存储器控制器I2C总线等,可以降低模块组成开销。通过PCI配置空间的访问简化了硬件逻辑、驱动的设计。PCI局部总线的使用使系统的结构更加明晰,易于扩展为分布式系统,通过对模块的实现可加深对PowerPC体系结构、PCI总线的了解。     

空载脉冲多普勒跟踪雷达数字信号处理机的设计和实现

分析了准连续波三通道雷达接收机的特点,提出了一种先进的雷达数字信号处理机的实现方案。该方案采用了中频采样、高速 DSP和并行体系结构等先进技术。在系统实现层次上,分析了一些中频采样实现方法的局限,进而提出了适合准连续波雷达回波特点的采样滤波器的设计方法和采样频率选择公式。在硬件设计上,本系统采用了32位浮点 DSP--ADSP21060和相应的并行结构。     

ARM核SOC EP7312及基于EP7312控显系统的设计

随着更多的公司将32位ARM处理器集成到自己的产品中,ARM核SOC在越来越广泛的领域得到应用。本文系统地介绍了一种基于ARM核的SOC——EP7312,描述了它的整体结构、基本工作原理,以及在具体显控系统设计中的应用;对基于EP7312显控软硬件的设计作了较为详细的阐述。     

基于S3C44b0X服装绘图仪液晶显示开发

服装绘图仪的控制核心采用SAMSUNG公司S3C44b0X处理器,S3C44b0X为一般应用提供了高性价比和高性能的微控制器解决方案。介绍了将S3C44b0X内置LCD控制器进行重新配置,使其能驱动YXD-12864A液晶显示模块,并给出了该控制器与LCD硬件接口方法,经实验验证此方法的正确性。     

Carrier loop architectures for tracking weak GPS signals

The performance of various carrier recovery loop architectures (phase lock loop (PLL), Doppler-aided PLL, frequency lock loop (FLL), and Doppler-aided FLL) in tracking weak GPS signals are analyzed and experimentally validated. The effects of phase or frequency detector design, oscillator quality, coherent averaging time, and external Doppler aiding information on delaying loss of lock are quantified. It is shown that for PLLs the metric of total phase jitter is a reliable metric for assessing low C/N performance of the tracking loop provided the loop bandwidth is not too small (~> 5 Hz). For loop bandwidths that are not too small, total phase jitter accurately predicts carrier-to-noise ratio (C/N) at which loss of lock occurs. This predicted C/N is very close to the C/N predicted by bit error rate (BER). However, unlike BER, total phase jitter can be computed in real-time and an estimator for it is developed and experimentally validated. Total phase jitter is not a replacement for BER, since at low bandwidths it is less accurate than BER in that the receiver loses lock at a higher C/N than predicted by the estimator. Similarly, for FLLs operating at small loop bandwidths, it is found that normalized total frequency jitter is not a reliable metric for assessing loss of lock in weak signal or low C/N conditions. At small loop bandwidths, while total frequency jitter may indicate that a loop is still tracking, the Doppler estimates provided by the FLL will be biased.     

货桥锁机构系统磨损可靠性分析评估方法的研究

提高大型运输机货桥（货舱门）锁系统的磨损可靠度的计算方法,并结合Ｙ８Ｃ飞机进行了计算,效果较好。     

Design and implementation for a digital synchronous reluctancedrive

A systematic controller design for a synchronous reluctance drive system is presented. This controller consists of two parts: a forward-loop H^∞ controller to improve the transient response, and a load compensator to reduce the load disturbance. Based on a simplified model of the drive system, a control algorithm has been derived. Detailed analysis of the characteristics of the closed-loop system is presented. The effects of the parameter variations are also studied. A digital signal processor, TMS-320-C30, is used to implement the control algorithm. Both the speed control and the position control of the drive system can be implemented by using the proposed control method. Furthermore, all the control loops are executed by the digital signal processor. The system, as a result, is very flexible. The whole drive system performs well although its hardware is very simple. For speed control, the system can be operated at a speed as low as 1 r/min. For position control, the system can accurately control a one-axis table. In addition, the system also has good position tracking ability. Several experimental waveforms validate the simulated results     

Design and implementation of a robust controller for a synchronousreluctance drive

A robust controller design for a synchronous reluctance drive system is presented. Based on a simplified model of the system, a robust position controller has been derived. A digital signal processor (DSP), TNO-320-C30, is used to implement the control algorithm. Furthermore, all the current, velocity, and position control loops are executed by the DSP. The system, as a result, is very flexible. Although the hardware circuit of the system is very simple, the synchronous reluctance drive system can accurately control a one-axis table. In addition, the system also has good transient response, load disturbance response, and tracking ability. Several experimental results validate the theoretical analysis     

Space systems general-purpose processor

The requirements for this processor were established using the experience of the hardware and software designers in the APL Space Department. The use of commercial hardware and software products, combined with an error- and fault-tolerant architecture, resulted in a low-cost design without adversely affecting overall reliability. The processor's architecture and mechanical design, and hardware and software test and validation methods are described.     

FPGA-based adaptive tracking estimation computer

We describe an FPGA-based adaptive tracking estimation computer (FATEC) for a multiple target tracking (MTT) radar system. Its design is centered around a small processor core customized according to the requirements of tracking application, to run the main control program and provide software flexibility, with a number of tracking algorithms (models) implemented in hardware-type functional units, in order to meet the timing requirements of the application. The FATEC approach provides combination of software flexibility, hardware efficiency, and functional adaptivity of implementation of application-specific computers for the other applications of a similar type, enabling various partitioning options between the software and the hardware parts of the solution