全并行结构FFT的FPGA实现

提出了一种基于FPGA实现的全并行结构FFT设计方法,采用X IL INX公司最新器件V irtex II P ro,用硬件描述语言VHDL和图形输入相结合的方法,在ISE 6.1中完成设计的输入、综合、编译及布局布线,并用M od-e lS im和M atlab对设计作了联合仿真。结果表明,通过利用FPGA器件中大量的乘法器、逻辑单元及存储器等硬件资源,采用全并行加流水结构,可在一个时钟节拍内完成32点FFT运算的功能,设计最高运算速度可达11ns,可实现对高速A/D采样数据的实时处理。

Full Parallel FFT Based on FPGA

A full parallel FFT based on the field programmable gate array(FPGA) is presented.By using FPGA VirtexII Pro,32-point full parallel FFT is realized in a single FPGA integrated circuit(IC).In the design,an mixed input method of VHDL and the graphic input is used.Then,the design is performed with synthesized,translated,route,etc.functions in the ISE6.1 software.After the route and place(R&P) is joined to an single FPGA IC,the full parallel FFT is co-simulated in ModelSim and Matlab software.Results show that by using luxuriant logic cells,RAM,ROM and DSP blocks in FPGA,VirtexII Pro and 32-point full parallel FFT can be realized in a single FPGA chip.The whole 32-point FFT computation can be completed in only one clock cycle.The operational system clock period can reach 11 ns.