FPGA设计中跨时钟域信号同步方法

随着FPGA系统设计的复杂化,系统内部的各个功能模块往往需要工作在不同频率的异步时钟域中,因此系统内核心功能模块与外设的通信设计无法避免地会涉及到跨时钟域的数据与信号的传递问题。尽管跨时钟域的同步问题并不属于FPGA系统设计领域的新问题,但是随着多时钟域系统的常见化和复杂化,使得跨时钟域同步这一要求具备了新的重要意义。在对跨时钟域设计中容易出现的亚稳态现象及其造成的影响进行简要概述与分析的基础上,为了减小亚稳态发生的概率和降低系统对亚稳态错误的敏感程度,提出了四种跨时钟域同步的解决方案,较为详细地阐述了设计方案,对设计进行了评估与分析,并给出了优化设计。

Method of Signal Synchronization of Cross-Clock Domain in Design of FPGA

With the complication of FPGA design ,the different modules in the design always work in the asynchronous clock domains .So the core module in the system has the problem of cross-clock domain when communicating with other modules .The cross-clock domain design becomes more and more impor-tant with complication of the design .The paper firstly introduces some basic concepts and elements of the metastable state occurred in the cross-clock domain design and its infection .In order to reduce the proba-bility of the metastable state ,this paper presents four FPGA-based synchronous units in detail and makes some discuss on the mend of the design .The performances analysis ,simulation and synthesis result is giv-en at the end of this paper .