| 一种纠3错BCH译码器的FPGA设计 |
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| 作者姓名： | 张国华 王菊花 |
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| 作者单位： | 西安电子科技大学ISN国家重点实验室，西安空间无线电技术研究所 |
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| 摘 要： | 文章基于一种较新颖的纠3错BCH码逐步译码算法和结构原型,提出了BCH译码器的完整实用化结构,采用FPGA设计并实现了纠3错BCH(31,16)译码器。该译码方案的特点是主体结构通用、资源占用少、运行速度高,非常适合于需要对传输帧的帧头实施特殊保护的数据传输应用场合。
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| 关 键 词： | BCH译码 纠3错 FPGA |
An FPGA-based decoder for triple-error-correcting BCH codes |
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| Authors: | Zhang Guohua Wang Juhua |
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| Institution: | Zhang Guohua1,2 Wang Juhua2 |
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| Abstract: | Based on a novel step-by-step decoding algorithm and its structure prototype for triple-error-correcting BCH codes,a complete and practical structure for BCH decoder is presented and an FPGA-based BCH(31,16) decoder designed.The decoding scheme is characterized by universal core structure,small device utilization cost and high speed,and thus are very suitable for the data transmission applications where the frame header needs a special protection from the corruption by noises. |
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| Keywords: | BCH decoding Triple-error-correcting FPGA |
| 本文献已被 CNKI 维普 等数据库收录！ |
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