| 具有SDRAM容错和检错功能的PowerPC 高性能处理单元设计 |
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| 引用本文： | 韩传冰,朱家强,朱纪洪.具有SDRAM容错和检错功能的PowerPC 高性能处理单元设计[J].航天控制,2005,23(5):46-51. |
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| 作者姓名： | 韩传冰 朱家强 朱纪洪 |
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| 作者单位： | 韩传冰（清华大学智能技术与系统国家重点实验室,北京,100084）
朱家强（清华大学智能技术与系统国家重点实验室,北京,100084）
朱纪洪（清华大学智能技术与系统国家重点实验室,北京,100084） |
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| 摘 要： | 介绍一款PowerPC架构的高性能嵌入式处理单元设计.利用PowerPC体系结构内建的差错检测和报告机制,采用CPLD设计和实现了三模冗余(TMR)SDRAM存储器模块,不但提供高速存储器的容错能力,还具有差错检测能力,提高了处理单元的可靠性.介绍一个分布式容错计算机的实例,并分析了该方案的优点.
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| 关 键 词： | PowerPC 嵌入式计算机 SDRAM 容错 检错 |
| 文章编号： | 1006-3242(2005)05-0046-06 |
| 修稿时间： | 2005年5月23日 |
A PowerPC High Performance Processing Unit Design with Fault-tolerant and Error-detectable SDRAM |
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| Han Chuanbin Zhu Jiaqiang Zhu JihongState Key Laboratory of Intelligent Technology and Systems,Tsinghua University,Beijing.A PowerPC High Performance Processing Unit Design with Fault-tolerant and Error-detectable SDRAM[J].Aerospace Control,2005,23(5):46-51. |
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| Authors: | Han Chuanbin Zhu Jiaqiang Zhu JihongState Key Laboratory of Intelligent Technology and Systems Tsinghua University Beijing |
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| Institution: | Han Chuanbin Zhu Jiaqiang Zhu JihongState Key Laboratory of Intelligent Technology and Systems,Tsinghua University,Beijing 100084 |
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| Abstract: | A high performance embedded processing unit of PowerPC architecture is designed.Based on the built-in error detection and reporting mechanism of the PowerPC architecture,a SDRAM module with triple-modular-redundancy(TMR) is implemented using VHDL.The scheme not only provides SDRAM fault-tolerance capability,but also makes full use of the error handling mechanism of the PowerPC architecture,thus the dependability of the unit increases.An example of distributed fault tolerant computer system is provided and the advantage of the adoption of the PowerPC processing unit introduced is analyzed.Subject terms PowerPC Embedded computer SDRAM Fault tolerance Error detection |
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| Keywords: | PowerPC Embedded computer SDRAM Fault tolerance Error detection |
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