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基于1394网络的分布式组合导航系统时序建模与仿真
引用本文:梁兆鑫,王涛,赵喆,陈银超,杨朝旭. 基于1394网络的分布式组合导航系统时序建模与仿真[J]. 航空工程进展, 2021, 12(1): 152-158
作者姓名:梁兆鑫  王涛  赵喆  陈银超  杨朝旭
作者单位:航空工业成都飞机设计研究所 飞控部,成都 610073;航空工业成都飞机设计研究所 飞控部,成都 610073;航空工业成都飞机设计研究所 飞控部,成都 610073;航空工业成都飞机设计研究所 飞控部,成都 610073;航空工业成都飞机设计研究所 飞控部,成都 610073
摘    要:总线拓扑完整是基于 1394 总线网络的分布式组合导航系统正常、可靠工作的必然要求,为了确保各传感器节点信息的可靠传输,必须在系统工作前进行总线完整性检查,以排除节点或线缆故障可能对系统造成的不利影响。导航计算机在执行总线完整性检查程序时,总线控制器的时钟源将发生切换,这会带来一定的时序问题。针对分布式组合导航系统在某次 1394b 总线完整性检查过程中出现的虚警故障,通过理论分析和建模仿真,对故障时刻的系统运行时序和虚警原因进行探究。结果表明:在进行总线完整性检查时,组合导航计算机与总线控制器时钟异步导致组合导航计算机软件相邻两周期读取 DPRAM 中同一片缓存是系统报出虚警的根本原因。

关 键 词:分布式组合导航系统  1394b总线  时序建模与仿真
收稿时间:2020-09-18
修稿时间:2020-12-21

Modeling and Simulation of Timing Sequence of Distributed Integrated Navigation System Based on 1394 Network
Zhaoxin Liang,Tao Wang,Zhe Zhao,Yinchao Chen and Zhaoxu Yang. Modeling and Simulation of Timing Sequence of Distributed Integrated Navigation System Based on 1394 Network[J]. Advances in Aeronautical Science and Engineering, 2021, 12(1): 152-158
Authors:Zhaoxin Liang  Tao Wang  Zhe Zhao  Yinchao Chen  Zhaoxu Yang
Affiliation:Chengdu Aircraft Design and Research Institute,Chengdu Aircraft Design and Research Institute,Chengdu Aircraft Design and Research Institute,Chengdu Aircraft Design and Research Institute,Chengdu Aircraft Design and Research Institute
Abstract:To ensure the reliable operation of the bus network for distributed systems, a bus network checking procedure should be made before the operation of the system to eliminate the influence of a faulty node or faulty cables. However, a timing problem may occure during the checking procedure, when the source clock of the bus controller switched. Base on a false alarm during the checking procedure for a distributed integrated navigation system, the author explored the causes and timing sequence of the false alarm by theoretical analysis and simulation. The research shows that the asynchronous clock between the integrated navigation computer and the bus controller causes the software of the integrated navigation computer to read the same cache in DPRAM in two adjacent cycles, which is the root cause of false alarm.
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