基于联合映射的高速数传发射机设计及其查找表法实现

根据高速数传发射机的要求,提出基于联合映射的高速卫星发射机设计及基于查找表的FPGA(F ieldProgramm ab le Gate Array,现场可编程门阵列)硬件实现方案。该方法将发射机中数字部分的TCM编码和成形滤波一起设计,将多个卷积相乘项相加后再量化,减少了量化次数,提高了量化信噪比。并根据FPGA芯片内部结构设计硬件实现方案,符合SOC(System of Ch ip)的趋势。用片内的BLOCKRAM精心设计查找表,在X ILINX公司25万门芯片VIRTEX2-250中就能实现此方案。MODELSIM的时序仿真结果表明可支持高达200Mb it/s的数据。文章结尾针对未来更高速率的高速数传发射机给出了一种通用硬件实现方法。

The Design of the Transmitter Based on the Joint Mapping in the Satellite High-speed Transmission and Its Look-up Table Implementation

This paper puts forward a design method of the high speed satellite transmitter based on the joint mapping according to the demand for high speed TCM8PSK transmitter and the FPGA implementation scheme based on look-up(table.)The method designs the digital parts of satellite transmitter together including TCM coding and shaping filtering,so it could be realized in the FPGA of small scale.The project was implemented in the VIRTEX2-250 of XILINX Corporation and proved correct through MODELSIM timing simulation.This paper presents a general hardware implementation way of the future high speed satellite transmitter in the end.