一种基于矩阵分裂的QC-LDPC码Log-BP译码方法

 针对高码率的准循环低密度奇偶校验码（QC-LDPC）提出了一种新的高效的log-BP部分并行译码结构，它通过矩阵分裂，将原监督矩阵分裂成多个小的矩阵，使原本的校验节点更新运算被拆分成多次处理，有效地降低了BP迭代运算的复杂度；通过组织不同小矩阵校验节点更新运算与变量节点更新运算的先后顺序，可以使不同小矩阵的校验节点更新运算与变量节点更新运算同时进行，从而提高译码器的译码速率。该方法既适用于非规则码，也适用于规则码。实验结果表明，与现有的log-BP译码方法相比，在相同的码速率下，校验节点更新单元（CNU）与变量节点更新单元（VNU）规模总量减小1/3；在相同的硬件资源下，译码速率提高1/3，另外该方法使CNU与VNU结构趋于对称，有利于设置更少的流水线级数，获得更好的时钟性能。

A Log-BP Decoding Method of Quasi-cyclic Low Density Parity Check Code Based on Matrix Split

A partly parallel decoding structure for quasi-cyclic low density party check code (QC-LDPC) is presented. In this method, the original check matrix is split into several smaller ones, thus the check node update unit (CNU) is decomposed into multiple parallel units, which brings in great hardware resource reduction. By organizing the sequence of check node updating process and variable node updating process, they can be carried out at a same time of different small matrixes, thus the decoding rate of the decoder is improved. This method may be applied not only to irregular LDPC code, but also to the regular one. The implementation result indicates that comparing with the log-BP decode method in common use, the presented method can reduce the logic core sizes of the CNU and variable node update unit (VNU) by approximately 1/3 under the same bit-rate or can improve bit-rate by approximately 1/3 under the same logic core size. Furthermore, this method makes the CNU more symmetric with the VNU, so that the design can gain higher timing performance by inserting fewer stages of pipelines.