基于CPS协同的微系统电源信号完整性设计

裸芯片die、硅通孔TSV(Through Silicon Via)硅转接板、高温共烧陶瓷HTCC(High Temperature Co-fired Ceramics)管壳等多材质多基板立体堆叠和高密度集成的微系统封装,因空间极度有限、跨尺度立体转换的失配、电磁效应的耦合,低电压大电流电源的电源分布网络PDN(Power Distribution Network)和GHz高速信号的通道设计成为难题。贴合微系统封装尺度越来越接近芯片尺度的特点,以及微系统模块的系统应用需求,研究了基于芯片、封装、系统CPS(Chip-Package-System)协同设计仿真的方法。针对核心电源PDN的设计,采用芯片功耗模型CPM(Chip Power Model),结合TSV硅基板、HTCC管壳、PCB三级去耦电容网络的布放和协同优化,有效降低了电源纹波,保证了电源完整性。针对高速信号通道设计,基于电磁场和电路结合的仿真,将芯片电特性配置与封装互连的拓扑匹配协同优化,封装与板级应用协同优化,保证了信号完整性,且不对封装版图和工艺提出严苛要求。

Power and signal integrity design of microsystem based on CPS co-design

High-integrated package of microsystem is based on multi-materials and substrates including die, TSV interposer, HTCC envelope etc. The design of PDN for low-voltage and high-current power supply and interconnect for high-speed signal becomes difficult, due to extremely limited space, mismatch of multi-scale structures and coupling of electromagnetic effects. Taking full account of the approaching scales of microsystem package and chip, and aiming at the application of microsystem in larger system, this paper focus on the CPS co-design and co-simulation method. For the PDN design of the core power, the CPM has been used to simulate the power ripple. Decoupling capacitor networks on TSV substrate, HTCC substrate and PCB have been assigned and co-optimized to realize the stable and clean power supply. For the interconnect design of high-speed signal, coupled field-circuit method has been used to model the package interconnect and analyze the time domain waveform. The configuration of chip electrical characteristics and design of signal interconnect have been balanced to gain the signal integrity. CPS co-design method can effectively utilize the limited space to improve the performance of microsystem.