SOI工艺抗辐照SRAM型FPGA设计与实现

为提升SRAM型FPGA电路块存储器和配置存储器抗单粒子翻转性能，本文提出一种脉冲屏蔽SRAM单元结构。该结构通过在标准的六管单元中加入延迟结构,增大单元对单粒子事件响应时间，实现对粒子入射产生的脉冲电流屏蔽作用。以64k SRAM作为验证电路进行单粒子翻转性能对比，电路的抗单粒子翻转阈值由采用标准六管单元的抗单粒子翻转阈值大于25 MeV·cm 2·mg -1 提升至大于45 MeV·cm 2·mg -1 ，加固单元面积较标准六管单元增大约21.3%。30万门级抗辐照FPGA电路通过脉冲屏蔽单元结合抗辐照SOI工艺实现，其抗辐照指标分别为：抗单粒子翻转阈值大于37.3 MeV·cm 2·mg -1 ，抗单粒子锁定阈值大于99.8 MeV·cm 2·mg -1 ，抗电离总剂量能力大于200 krad(Si)。

A Radiation Hardened SRAM based FPGA Implemented in SOI Process

A pulse shielded SRAM cell is proposed for increasing the SEU performance which is used in block RAM (BRAM) and configuration memory of FPGAs. The pulse current from an incident particle is shielded because of the increasing single event response time for a SRAM cell. The SEU performance is verified by the 64k SRAMs with SEU threshold improving from 25 MeV·cm 2·mg -1 to 45 MeV·cm 2·mg -1 at only 21.3% additional cost of the SRAM cell area. By adopting the pulse shielded SRAM cell and radiation hardened process, the 300,000-gate FPGA possesses radiation features: SEU threshold higher than 37.3 MeV·cm 2·mg -1 ; SEL threshold higher than 99.8 MeV·cm 2·mg -1 and total dose tolerance higher than 200 krad(Si) respectively.