基于FPGA高效实现FIR滤波器的研究

文章对FPGA中FIR滤波器的高效实现进行了研究。介绍了流水线技术的原理和应用,比较了整数的CSD表示和根据FPGA结构加以改进的最优表示,提出了FIR滤波器高效实现的措施。最后以具体实例说明了这些措施的可行性和有效性。

The Research on an Efficient Implementation of FIR Filter on FPGA

The efficient implementation of FIR filters is researched on FPGA.We introduce the principle and the application of the pipelined technology.Then the CSD representation of integer is introduced,followed by an improved optimum representation according to the FPGA structure.The efficient measures to implement FIR filters are brought forward.We offer an example to prove these measures are feasible and efficient at last.