| PLC栈缓冲ASIC芯片的设计与实现 |
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| 引用本文： | 谭军安,尹宝林.PLC栈缓冲ASIC芯片的设计与实现[J].北京航空航天大学学报,1992(3):57-63. |
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| 作者姓名： | 谭军安 尹宝林 |
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| 作者单位： | 北京航空航天大学计算机科学与工程系
(谭军安)，北京航空航天大学计算机科学与工程系(尹宝林) |
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| 摘 要： | 存贮管理是计算机体系结构的重要组成部分。对于Prolog和Lisp两种人工智能语言来说,它们的操作大多都是针对栈式存贮区进行的,因此一个高速的栈控制器将有效地提高它们的执行速度。本文简要介绍了Prolog/Lisp协处理器(PLC)栈缓冲机制的结构、原理以及栈缓冲专用芯片SC(Stack Controller)的设计方法和实现技术,为Prolog和Lisp语言的高效执行提供了一个性能价格比较高的存贮系统。
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| 关 键 词： | 空间分块 循环编址 寄存器切换 |
THE DESIGN AND IMPLEMENT OF ASIC CHIP FOR PLC STACK BUFFER |
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| Tan Junan Yin Baolin.THE DESIGN AND IMPLEMENT OF ASIC CHIP FOR PLC STACK BUFFER[J].Journal of Beijing University of Aeronautics and Astronautics,1992(3):57-63. |
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| Authors: | Tan Junan Yin Baolin |
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| Institution: | Dept. of Computer Sci. and Eng. |
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| Abstract: | Memory management is an important part of computer architechure.On account of artificial intellegence language such as Prolog and Lisp,their operation most deal with stack memory.As a result,a high speed stack controller will enhance the executing of Prolog and Lisp validly.In this paper,the stack controller(SO is briefly introduced about its structure and principles of PLC stack buffer mechanism as well as the designing and implementing of ASIC chip to provide a excellent memory system with high performance/cost ratio. |
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| Keywords: | space separating cycle addressing register toggling |
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