DVB-S接收机中时钟与载波同步的FPGA实现

介绍数字滤波平方定时算法和硬判决型科斯塔斯环的基本原理,并基于这两种算法,用可编程器件FPGA实现DVB-S接收机中的采样时钟同步和载波同步。整个设计基于XILINX公司的ISE平台,用VHDL编程语言通过逻辑综合和仿真在xc3s2000 FPGA芯片上实现。

FPGA Realization of Clock and Carrier Synchronization in the DVB-S Receiver

This paper presents the principle of digital filter square clock synchronization method and hard decision Costas phase lock loop.The design of sample clock and carrier synchronization with FPGA in the DVB-S receiver is realized based on the two methods.The whole design is implemented in the xc3s2000 FPGA chip with VHDL on the ISE platform of XILINX company after the synthesis and simulation.