高性能的标准单元库设计

从仿真和流片两个方面对标准单元库的验证方法进行了研究.在仿真方面,提出了采用静态时序分析工具和SPICE仿真工具对单元的估算值和仿真结果进行比较分析的方法来验证,同时还给出了具体的操作步骤实例.在流片验证中,提出了一种非常有效的电路结构.这种电路结构不但能够准确验证时序,还能极大地减少PAD数量;最重要的特点是:该电路能够完全避免PAD和非被测单元的引入带来的额外延迟,从而得到准确的被测单元延迟.

Validation of Standard Cell Library

The topic of the paper is to validate the Standard cell library from the two following facets: the simulation and tap out.In the simulation,Static timing analysis tool PrimeTime will be used to compute the delay, meanwhile HSPICE will also be used to simulate the delay.Comparing their delays,it will make sure whether the delay of cell is accurate.A example of the process was also given.The validation of tap out chip is accurate method.In tap out,a special circuit is present,which not only accurate enough for testing the chip but also greatly reduce the number of PADs,and the most important thing is that it can completely eliminate the PAD delay.