Top-Down设计法在转发器本振置数及监测电路设计中的应用

介绍一种高效、简洁的 FPGA/ PL D设计方法—— Top- Down设计法 ,将其与传统的设计方法进行了比较 ,并对其优点进行了详细的叙述。通过基于 PL D的转发器本振置数和监测电路的设计 ,举例说明此方法在工程设计中的应用

Application of Top-Down Method in the Design of Number-setting and Monitoring Circuit of the Transponder Based on EPLD

An efficient and simple FPGA/PLD designing method--Top-Down designing method is presented and compared with the traditional one. It's outstanding characteristics are described detailedly in this paper too. The application of this method in the engineering designing aspect is illustrated by the design of the number-setting and monitoring circuit of the transponder oscillator based on EPLD.