基于A2-RO电路版图填充的硬件木马抗植入方法

集成电路芯片制造过程中，攻击者可以利用电路版图中的空白区域植入硬件木马。为此，提出了一种基于A2-RO电路版图填充的硬件木马抗植入方法, 以减小电路版图中的空白区域为防护目标，设计了能够动态监测稀有节点翻转情况的功耗表征结构A2-RO，并提出了迭代填充算法及路径构建算法，通过在电路版图的空白区域中智能化地构建A2-RO电路，提高了电路的安全防护水平。基于SMIC 180 nm工艺，以ISCAS’85和ISCAS’89中的基准电路作为研究对象进行仿真验证。仿真结果表明:版图填充后，芯片的面积利用率提高至95%以上，剩余空白区域无法填充最小尺寸的标准单元。A2-RO电路移除攻击后的侧信道电流变化值为1.921 mA，有效实现了对版图空白区域的防护。版图填充的额外布线资源开销可控制在7%以内，对关键路径延时的影响在1.2%以内。 

A hardware Trojan insertion prevention method based on layout filling with A2-RO circuit

During the chip manufacturing process of integrated circuits, attackers can use blank areas in the circuit layout to implant hardware Trojans. For this reason, this paper proposes a method to prevent inserting hardware Trojans by filling the layout with A2-RO circuit. The goal of protection is reducing the blank areas in the circuit layout. This paper designs the power consumption characterization structure named A2-RO that can dynamically monitor the flipping of rare nodes. And the iterative filling algorithm and the path construction algorithm are proposed. We construct the A2-RO circuit in the blank area intelligently to improve the security level of the circuit. We apply the benchmark circuits in ISCAS'85 and ISCAS'89 as the research object for simulation based on the SMIC 180 nm process. The simulation results show that after filling the layout, the area utilization rate of the chip will be increased to more than 95%, and the remaining blank area cannot be filled with the smallest standard cell. After the removal attack of A2-RO circuit, the change of side channel current is 1.921 mA. The A2-RO circuit can effectively protect the blank areas. The additional routing overhead for layout filling can be controlled within 7%, and the impact on the critical path delay is within 1.2%.