| 一种宽带高速跳频载波频综结构的设计 |
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| 引用本文： | 黄正婧,张晓林,常啸鸣. 一种宽带高速跳频载波频综结构的设计[J]. 飞行器测控学报, 2012, 0(1): 42-46 |
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| 作者姓名： | 黄正婧 张晓林 常啸鸣 |
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| 作者单位： | 北京航空航天大学电子信息工程学院 |
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| 摘 要： | 将DDS（直接数字合成）与PLL（锁相环）频率合成技术相结合,采用多环并列流水线结构,设计出混合扩/跳频系统的载波频率综合单元。利用DDS技术可实现频率分辨率高、转换时间快等要求,利用PLL技术可实现杂散抑制性能高、扩展宽带等要求,并采用多环并列硬件结构保证了系统的跳变速度和宽频带指标。经闭环测试平台的测试,系统达到350～1800MHz带宽可变,频率跳变速度10 000跳/s可变,杂散抑制优于-80dBc。文章首先给出详细的硬件设计方案及其实现,同时理论分析了个各项指标的优化,最后给出闭环测试平台的搭建以及最终测试结果。
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| 关 键 词： | 直接数字合成（DDS） 锁相环（PLL） 宽频带 高跳速 直扩／跳频（DS／FH） 闭环测试 |
Design of the Structure of a High Frequency Hopping Rate Broadband Carrier Frequency Synthesizer |
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| HUANG Zhengjing,ZHANG Xiaolin,CHANG Xiaoming. Design of the Structure of a High Frequency Hopping Rate Broadband Carrier Frequency Synthesizer[J]. Journal of Spacecraft TT&C Technology, 2012, 0(1): 42-46 |
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| Authors: | HUANG Zhengjing ZHANG Xiaolin CHANG Xiaoming |
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| Affiliation: | (College of Electronic Information Engineering,Beihang University,Beijing 100191) |
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| Abstract: | A DDS+PLL(Direct Digital Synthesizing + Phase-Locked Loop) carrier frequency synthesizer is designed with a parallel multi-ring pipeline architecture.DSS technology provides high frequency resolution and fast frequency conversion while PLL technology provides high spurious suppression ratio for spread spectrum.The parallel multi-ring pipeline hardware architecture ensures the frequency hopping rate and bandwidth specifications of the system.As demonstrated by closed-loop tests,the carrier frequency synthesizer features a variable bandwidth of 350-1800MHz and a variable frequency hopping rate up to 10000 hops/s,and its spurious suppression is better than-80dBc.Hardware design and implementation of the system is described in detail and theoretical analysis for optimization of different specifications is given.Setup of the closed-loop tests as well as the final test results are provided. |
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| Keywords: | Direct Digital Synthesizing(DDS) Phase-Locked Loop(PLL) Broadband High Frequency Hopping Rate Direct Spread Spectrum/Frequency Hopping(DS/FH) Closed-Loop Test |
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