| 计算机RAM检错纠错电路的设计与实现 |
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| 引用本文： | 刘淑芬,崔星.计算机RAM检错纠错电路的设计与实现[J].航天控制,2003,21(4):59-67. |
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| 作者姓名： | 刘淑芬 崔星 |
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| 作者单位： | 北京控制工程研究所,北京,100080 |
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| 摘 要： | 分析了在空间环境下影响RAM可靠性的主要因素及主要故障模式,介绍了利用FPGA实现RAM 检错纠错电路的方法,给出了仿真结果,并将此方法同用中小规模集成电路实现RAM EDAC的方法进行了比较。
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| 关 键 词： | 计算机 RAM EDAC 设计 仿真 FPGA |
| 修稿时间： | 2003年6月6日 |
Design and Realization of Error Detection and Correction Circuit for Computer RAM |
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| Liu Shufen,Cui Xing Beijing Institute of Control Engineering,Beijing.Design and Realization of Error Detection and Correction Circuit for Computer RAM[J].Aerospace Control,2003,21(4):59-67. |
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| Authors: | Liu Shufen Cui Xing Beijing Institute of Control Engineering Beijing |
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| Institution: | Liu Shufen,Cui Xing Beijing Institute of Control Engineering,Beijing 100080 |
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| Abstract: | In this paper, the main factors affecting the reliability of RAM as well as the
failure modes in the space environment are demonstrated. The RAM EDAC circuit implement-
ed by FPGA is introduced. At the same time, it is compared with that realized by small and
medium-scale integrated circuits. Further more, the simulationt rdsults are given. |
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| Keywords: | Computer SRAM EDAC Simulation |
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