| 高速电路PCB设计与仿真 |
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| 引用本文： | 张瑞锋,夏刚,王汀. 高速电路PCB设计与仿真[J]. 导航与控制, 2010, 9(1): 39-42 |
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| 作者姓名： | 张瑞锋 夏刚 王汀 |
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| 作者单位： | 北京航天控制仪器研究所,北京,100039;北京航天控制仪器研究所,北京,100039;北京航天控制仪器研究所,北京,100039 |
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| 摘 要： | 在某测试系统核心板PCB设计中,基于IBIS模型,利用Cadence软件对SDRAM和主CPU间的高速信号进行信号完整性仿真,依靠仿真结果指导PCB设计,对关键网络的走线长度以及拓扑结构等做预先设计,有助于提高系统性能、减小失败风险和缩短开发周期。
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| 关 键 词： | 高速PCB设计 信号完整性Cadence 时序分析 |
High Speed Circuit PCB Design and Simulation |
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| ZHANG Rui-feng,XIA Gang and WANG Ting. High Speed Circuit PCB Design and Simulation[J]. Navigation and Control, 2010, 9(1): 39-42 |
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| Authors: | ZHANG Rui-feng XIA Gang WANG Ting |
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| Affiliation: | Beijing Institute of Aerospace Control Device;Beijing Institute of Aerospace Control Device;Beijing Institute of Aerospace Control Device |
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| Abstract: | The paper covered the usage of Cadence tool for the PCB design of SDRAM memory interface in one of testing system. By simulating the critical signal nets based on IBIS model, the PCB design rules such as trace length and net topology were determined. This helped to improve the system performance, reduce the fail risk and development period. |
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