一种星载计算机秒中断间隔可控的校时方法

传统的星载计算机时间维护主要由软件实现，为了避免校时过程中秒中断间隔过小或过大，软件需要通过复杂的逻辑和算法对外部计时器Intel 82C54芯片进行多次操作才能实现一次校时，较容易出错，且占用CPU机时较多。随着未来航天器智能处理的任务越来越多，CPU机时越来越紧张，为了将CPU从繁琐的校时操作中解放，提出了一种基于FPGA的秒中断间隔可控的校时方法。通过FPGA逻辑电路设计星时计时器，利用秒中断间隔约束条件设计校时触发条件，当满足校时触发条件时，FPGA逻辑电路自动实现校时操作，很好地解决了校时过程中秒中断间隔过大或过小的问题，节约了CPU机时。该校时方法已在多台星载计算机上应用，取得了较好的效果。

A time calibration method with controllable second interrupt interval for on board computers

The traditional on board computer time maintenance is mainly implemented by software. In order to avoid the second interrupt interval being too small or too large during the time calibration process, the software needs to perform multiple operations on the external timer Intel 82C54 chip through complicated logic and algorithms. It is very likely to make mistakes, and it takes a lot of CPU machine cycles. With the increasing tasks for spacecraft intelligent processing in the future, the CPU machine cycle becomes more and more scarce. In order to free the CPU from the cumbersome time calibration operation, a time calibration method with controllable second interrupt interval based on FPGA was proposed. The satellite time timer was designed with the FPGA logic circuit. And the trigger condition of time calibration was designed by using the constraint condition of second interrupt interval. When the trigger condition of time calibration is met, the FPGA logic circuit automatically executes the time calibration operation, which solves the problem of too large or too small second interrupt intervals during the time calibration process, and saves a lot of CPU machine cycles. The time calibration method proposed has been applied on several on board computers, and has achieved the expected goal.