| 基于 FPGA 的 DVI 视频接收器设计 |
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| 引用本文： | 汪溢,于乐.基于 FPGA 的 DVI 视频接收器设计[J].航空电子技术,2012(1):30-33,38. |
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| 作者姓名： | 汪溢 于乐 |
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| 作者单位： | 1. 海军驻上海地区航空军事代表室,上海200233
2. 中国航空无线电电子研究所,上海200233 |
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| 摘 要： | 针对目前 DVI 视频传输的大规模应用,给出了一个符合 DVI1.0规范的基于 Xilinx Virtex-5 FPGA的 DVI视频接收器的实现方法.该方法利用简单的电阻电容和 FPGA内置数字控制阻抗(DCI)功能来实现TMDS电平的转换,利用 FPGA 内置的 DDR 和 ISERDES 实现 DVI 数据的串并转换,利用 FPGA 内置时钟资源实现时钟恢复和相位调整,最后经过逻辑解码,输出并行带同步信号的视频数据
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| 关 键 词： | 数字视频接口(DVI) FPGA 最小化传输差分信号(TMDS) 接收器 |
DVI Receiver Design Based on FPGA |
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| WANG Yi,YU Le.DVI Receiver Design Based on FPGA[J].Avionics Technology,2012(1):30-33,38. |
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| Authors: | WANG Yi YU Le |
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| Institution: | 1.Aeronautical Military Representative Office Residentin Shanghai Region for the Narv Force,Shanghai200233,China;2.China National Aeronautical Radio Electronics Research Institute,Shanghai 200233,China) |
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| Abstract: | DVI video transfer protocol are widely used,as a result,the design method of DVI receiver on Xilinx Virtex-5 FPGA according to DVI 1.0 specification is presented.The TMDS standard is converted simply by resistor,capacitor terminations and build-in DCI in FPGA.The serial data is transferred to parallel by DDR and ISERDES module in FPGA.The clock is recovered and de-skewed by FPGA clock manager resources.Finally,parallel video data with sync signals is decoded. |
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| Keywords: | digital visual interface(DVI) FPGA transitionminimizeddifferential signaling(TMDS) receiver |
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