准循环LDPC码译码器的FPGA实现 |
| |
作者姓名: | 何庆涛 周正 葛建华 |
| |
作者单位: | 西安电子科技大学ISN国家重点实验室,西安710071 |
| |
基金项目: | 国家自然科学基金资助项目(60496316) |
| |
摘 要: | 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构,基于该部分并行结构在Altera公司的StratixII—EP2S90器件上验证并实现了DTMB标准中三种准循环低密度校验码的译码器。FPGA资源统计表明,在并行路数相同的情况下,采用该部分并行结构可以节省大约45%的逻辑单元。
|
关 键 词: | 低密度校验码 最小和算法 部分并行结构 译码器 |
An FPGA Implementation of QC-LDPC Decoder |
| |
Authors: | He Qingtao Zhou Zheng Ge Jianhua |
| |
Institution: | He Qingtao Zhou Zheng Ge Jianhua (National Key Lab. of ISN, Xidian University, Xi'an 710071 ) |
| |
Abstract: | A partially-parallel decoder architecture is proposed,which is not only suitable for different code-rates,but also can be used for both regular and irregular Quasi-Cyclic LDPC codes.Based on the architecture,a decoder for the three kinds of QC-LDPC codes in DTMB standard has been implemented on the FPGA device Altera StratixII-EP2S90.Statistical results show that about 45% of logic units can be saved by using the architecture. |
| |
Keywords: | LDPC Min-sum algorithm Partially-parallel architecture Decoder |
本文献已被 CNKI 维普 等数据库收录! |