基于多层有限元法的去耦电容设计

在高速板卡设计中,为了避免电路发生瞬变电流时产生不必要的电压波动,可通过放置去耦电容的方式减小电源分配网络（PDN）在某些频率下的阻抗。但大规模集成电路封装和板级结构的复杂性以及高驱动频率,导致选择和放置合适的电容器成为一个难题。遗传算法（GA）能够方便有效地进行去耦电容的选择和放置。文章采用遗传算法与多层有限元法（MFEM）结合的方法解决了降低电源分配网络阻抗的问题,通过实例验证了纵向元件与多层有限元相结合的方法的有效性。

Decoupling Capacitors Design Based on MFEM

The impedance of the PDN needs to be minimized in order to prevent unwanted voltage fluctuation at frequencies where current transient occur. PDN impedance can be reduced by placing decoupling capacitors which act as local current sources. However, selecting and placing the right capacitors at the right locations is hard because of the complexity of modem package and board structures, and high frequency. Genetic algorithm （GA） is customized for the selection and placement of decoupling capacitors. In this paper, the multilayer finite element method （MFEM） and GA were combined to solve the problem that decreasing the PDN impedances. A method of incorporating vertical circuit elements into MFEM was also validated by a test case, which proved the validity of the inclusion of vertical elements in MFEM and the effectiveness of the optimizer.