| DDS PLL电路中的频率规划 |
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| 引用本文： | 姚鸿飞,刘德喜,田立卿. DDS PLL电路中的频率规划[J]. 遥测遥控, 2007, 0(Z1) |
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| 作者姓名： | 姚鸿飞 刘德喜 田立卿 |
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| 作者单位： | 北京遥测技术研究所 北京100076 |
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| 摘 要： | 对DDS PLL电路中杂散的产生机理进行简要分析,在此基础上对系统进行频率规划,仔细设置DDS参考、DDS输出、混频器输入等处信号的频率。实验表明,文中所做的频率规划可以有效地降低输出信号的杂散,同时不影响系统其他性能。
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| 关 键 词： | DDS PLL 频率规划 |
Frequency Plan in DDS PLL Circuits |
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| Yao Hongfei,Liu Dexi,Tian Liqing. Frequency Plan in DDS PLL Circuits[J]. Telemetry & Telecontrol, 2007, 0(Z1) |
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| Authors: | Yao Hongfei Liu Dexi Tian Liqing |
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| Abstract: | The principle of frequency spurs in DDS(direct digital frequency synthesis) PLL(phase locked loop) circuits is briefly analyzed.Associated with the actual example,the frequency plan is addressed,and the signal frequency of the DDS reference,DDS output and mixer input is designed carefully.Measurements show that the frequency plan can efficiently reduce the spur level while it has no influence on other performances. |
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| Keywords: | DDS PLL Frequency plan |
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