基于多处理器高距离分辨力雷达算法并行实现

介绍了一个用于跟踪高速目标的基于8片ADSP-TS201 TigerSHARC处理器的实时信号处理机的并行实现.讨论了并行处理机整体结构设计,包括处理器间拓扑结构、通信、同步与控制等.实现并行系统的一个关键是将应用问题优化映射到目标处理机硬件的各个并行部件中,文中在考虑算法复杂度、可分解度、并行度的同时,综合处理机平台处理能力、实时性、处理器间通信量及运算负载的平衡性等因素,实现了算法流程到硬件平台的高效映射.在此基础上,重点研究了系统级、运算级和指令级的并行流水线设计方法,分析了利用SIMD(Single Instruction Multiple Data),静态超标量,BTB(Branch Target Buffer)等并行结构和处理机制对并行汇编指令进行高效的优化.实际的校飞试验验证了该处理机设计与实现方法的有效性、实时性和可靠性. 

Parallel algorithm realization of high range resolution radar based on multi-processor

An advanced real-time pulsed Doppler-pulse compressed radar signal processing system that managed to track targets with high velocity was implemented based on 8 ADSP-TS201 TigerSHARC processors.System structure designing was discussed,including DSP(digital signal processors) topology,communication,synchronization and control.In parallel system,it is crucial to optimize the mapping of problems onto parallel execute units of specific hardware platform.When implementing effective algorithm mapping,various factors were considered,such as algorithm complexity and resolvability,hardware process and real-time capability,and CPU load balance of communication and calculation tasks.Parallel design and optimization on both system and instruction levels were emphasized,while realizing system level optimization.Also parallel pipeline designing methodology was presented,including the pipelines both inside and between DSPs.With regard to the instruction level optimization,several parallel mechanisms such as SIMD(single instruction multiple data),static superscalar,BTB(branch target buffer) and space-time tradeoff were studied to optimize the system with extremely high performance,which was proved by the field experiment results.