伪随机时钟激励模块设计研究及应用

随着现场可编程逻辑器件（Field Programmable Gate Array，FPGA）验证水平的逐渐提高，对于测试平台（Testbench）中产生的时钟激励也提出越来越高的要求。目前，在Testbench中使用的时钟激励模块都是具有固定周期和固定占空比的激励信号，然而在现实条件下，时钟沿都具有一定的抖动，从而影响到时钟的占空比及瞬时频率。为了模拟时钟的这种实际特性，文章提出了一种基于伪随机算法实现的沿跳变的时钟激励模块，并将该模块用于高速计数器设计的实现验证，取得较好的验证效果。

Designing of a Pseudorandom Clock Stimulus Module

In the process of FPGA verification,most Clock stimulus modules used in testbenches are generating clock signals which have fixed period and fixed ratio.However,clock sourced by crystals or other real clock generating parts always have jitter,which influence the real time frequency.To simulate the characteristics of real clock signals,we have developed a designing of pseudorandom clock stimulus module which have pseudorandom clock edges which can be used in any testbenches edited with VHDL.Also in the artic...