首页 | 本学科首页   官方微博 | 高级检索  
     检索      

一种多核实时图像处理模块设计与实现
引用本文:王闯,贺莹,张晓曦,刘硕.一种多核实时图像处理模块设计与实现[J].航空计算技术,2017,47(4).
作者姓名:王闯  贺莹  张晓曦  刘硕
作者单位:航空工业西安航空计算技术研究所,陕西西安,710068
基金项目:国家自然科学基金重点基金项目资助
摘    要:实时图像处理能力是嵌入式系统中影响系统性能的核心因素.为充分挖掘多核DSP性能,从计算机系统结构的角度出发,开展对多核DSP实时图像处理体系结构的研究,设计了一种基于TMS320 C6678的实时图像处理模块.采用FPGA进行实时图像的采集和缓存,利用四线RapidIO高速接口完成FPGA与DSP之间的数据传输,并设计了四级图像缓冲流水处理结构,实现了图像采集、缓存、处理和发送的并行进行.设计了一套基于数据块共享的实时图像处理多核协同处理机制,可以充分利用C6678八个核的优势,实现对图像的实时处理.

关 键 词:多核DSP  FPGA  并行处理框架  实时图像处理

Design and Implementation of Multi-core Real-time Image Processing Module
WANG Chuang,HE Ying,ZHANG Xiao-xi,LIU Shuo.Design and Implementation of Multi-core Real-time Image Processing Module[J].Aeronautical Computer Technique,2017,47(4).
Authors:WANG Chuang  HE Ying  ZHANG Xiao-xi  LIU Shuo
Abstract:Real-time image processing ability is the key factor for visual applications ,especially embed-ded systems .To fully exploit the performance of multicore DSP ,this paper studies the architecture of real-time image processing in the light of computer architecture and designs a real -time image processing module based on TMS320C6678.Real-time image data stream is acquired and buffered by FPGA .Com-munication between DSP and FPGA is achieved by using four lane RapidIO interface .The hardware scheme of the processing in FPGA possesses a linear four-level pipeline architecture , which makes the operation of image acquisition ,buffering ,processing and transferring can be completed almost at the same time .A kind of shared memory interconnection method is proposed to solve the rapid inter-core communi-cation problems among C66xx cores and the system achieves up to real-time image processing speed fi-nally.
Keywords:multi-core DSP  FPGA  parallel processing framework  real-time image processing
本文献已被 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号