Fault self-repair strategy based on evolvable hardware and reparation balance technology

In the face of harsh natural environment applications such as earth-orbiting and deep space satellites, underwater sea vehicles, strong electromagnetic interference and temperature stress,the circuits faults appear easily. Circuit faults will inevitably lead to serious losses of availability or impeded mission success without self-repair over the mission duration. Traditional fault-repair methods based on redundant fault-tolerant technique are straightforward to implement, yet their area, power and weight cost can be excessive. Moreover they utilize all plug-in or component level circuits to realize redundant backup, such that their applicability is limited. Hence, a novel selfrepair technology based on evolvable hardware（EHW） and reparation balance technology（RBT） is proposed. Its cost is low, and fault self-repair of various circuits and devices can be realized through dynamic configuration. Making full use of the fault signals, correcting circuit can be found through EHW technique to realize the balance and compensation of the fault output-signals. In this paper, the self-repair model was analyzed which based on EHW and RBT technique, the specific self-repair strategy was studied, the corresponding self-repair circuit fault system was designed, and the typical faults were simulated and analyzed which combined with the actual electronic devices. Simulation results demonstrated that the proposed fault self-repair strategy was feasible. Compared to traditional techniques, fault self-repair based on EHW consumes fewer hardware resources, and the scope of fault self-repair was expanded significantly.     

基于FC光传总线的分布式容错系统组通信协议

分布式容错系统常用于构造高可靠的关键应用,其核心构件组通信协议(GCP)实现了带有可靠性语义的多对多的通信原语。本文主要讨论基于光纤通道(FC)总线用于分布式容错的组通信协议,探讨了使用冗余消息技术实现实时、可靠数据传输的方法,提出了将数据和控制消息分开处理来实现数据输入实时性和控制消息按因果顺序提交的算法,力求获得最大程度的并行性。提出并设计了基于领导者-跟随者的故障处理机制,利用两阶段事务处理协议实现故障处理中的视图同步和状态切换,给出了协议的设计原理和实现框架。最后给出了该协议在基于PowerPC单板计算机的三余度容错飞行控制计算机系统中的运行结果,并对该结果进行了简要分析。     

Optimal design of RTCs in digital circuit fault self-repair based on global signal optimization

Since digital circuits have been widely and thoroughly applied in various fields, electronic systems are increasingly more complicated and require greater reliability. Faults may occur in elec-tronic systems in complicated environments. If immediate field repairs are not made on the faults, elec-tronic systems will not run normally, and this will lead to serious losses. The traditional method for improving system reliability based on redundant fault-tolerant technique has been unable to meet the requirements. Therefore, on the basis of (evolvable hardware)-based and (reparation balance technology)-based electronic circuit fault self-repair strategy proposed in our preliminary work, the optimal design of rectification circuits (RTCs) in electronic circuit fault self-repair based on global sig-nal optimization is deeply researched in this paper. First of all, the basic theory of RTC optimal design based on global signal optimization is proposed. Secondly, relevant considerations and suitable ranges are analyzed. Then, the basic flow of RTC optimal design is researched. Eventually, a typical circuit is selected for simulation verification, and detailed simulated analysis is made on five circumstances that occur during RTC evolution. The simulation results prove that compared with the conventional design method based RTC, the global signal optimization design method based RTC is lower in hardware cost, faster in circuit evolution, higher in convergent precision, and higher in circuit evolution success rate. Therefore, the global signal optimization based RTC optimal design method applied in the elec-tronic circuit fault self-repair technology is proven to be feasible, effective, and advantageous.     

大型民机的非相似余度飞控计算机研究

 对中国自主研制的大型民机的余度飞行控制系统进行基础技术研究,设计了一套适合民机电传(FBW)系统的余度飞控计算机(FCC)新方案。提出了民机余度飞控计算机的2个设计准则：满足系统的可靠性指标和满足FO/FO/FO容错等级。然后根据这2个基本准则,给出了民机余度飞控计算机设计的7个建议,从而确定了民机余度飞行控制系统的余度数和余度结构：新型民机的余度飞行控制系统可采用非相似四余度,每个余度通道由两个支路构成比较监控结构,每个支路运行2套软件,保证软硬件系统的可靠性均衡。还确定了民机余度飞行控制系统的工作方式,使用Petri网分析了新方案的可靠性,并与B777和A320的余度飞控计算机进行了比较。     

非相似余度飞控计算机

从容错的角度介绍了Boeing777和A320的数字飞行控制计算机系统。Boeing777和A320的飞控计算机都采用了非相似的余度技术,能容忍软件和硬件的共态故障,但在每个计算机的功能分配和整个飞控计算机系统的余度结构编排等方面体现了各自的特点。用广义随机Petri网描述了Boeing777余度结构和容错动态过程,并进行了系统的可靠性计算和容错度分析。针对中国"大型飞机"容错飞控系统的设计作了分析和建议。     

存储系统中两级纠错编码方案设计与验证

针对恶劣空间环境设计了一种两级存储编码方案,以应对航天系统中存储单元发生多个单粒子翻转（SEU）错误的问题。方案设计的主要思想是根据简单低纠错编码组合出高容错编码,通过编码组合,使用字间编码来纠正字内编码无法纠正的错误,从而使存储系统更加可靠;对两级编码方案提出若干优化策略,以提高编解码性能,使得两级冗余编码效率接近于原始字内编码。实验结果表明,提出的两级冗余编码方案能够较好解决存储系统中发生多个单粒子翻转错误的问题。即与单一的字内编码相比,两级纠错编码方案能够大大降低星上存储系统出现不可修复的概率,保证了星上存储系统的可靠运行。     

空间模块化机械手系统容错控制系统研究

研究搭载在空间站或其他近地轨道航天器上的空间模块化机械手系统的容错控制系统.与地面应用环境相比较,空间特殊的应用环境存在许多不同,因而传统工业机械手系统的设计技术不能直接应用于空间机械手系统的设计.考虑到空间应用对系统质量、体积、功耗、研制费用和周期所提出的苛刻要求,主要采用COTS器件设计并实现该空间机械手系统的容错控制系统,介绍了系统的软硬件体系结构及其特点,最后给出系统的性能参数.在系统设计中采用许多已有的设计技巧与工程经验,具有高可靠性和工程实用性.     

基于低冗余度的传感器故障诊断研究

对于大型飞机来说,飞行控制系统各部件(包括传感器)多采用高余度的硬件配置来提高系统的任务可靠性,但对小型飞机来说,由于受重量、空间及费用等原因的影响,一些传感器不适合安装三余度或四余度传感器。对于二余度或单传感器来说,如何鉴别故障传感器或判断传感器是否发生故障较为困难。同样,传统的故障诊断与隔离方法并不能隔离三余度传感器系统中的多个故障。为了解决低冗余度传感器故障诊断问题,提出一种不依赖数学模型的奇偶方程方法与小波分析相结合的传感器故障诊断方法。     

Reliability analysis of fault-tolerant IMU architectures withredundant inertial sensors

A systematic reliability analysis procedure for evaluating fault-tolerant inertial measurement unit (IMU) architectures is described. The procedure is based on modeling the system architecture, the component reliabilities, and the redundancy management. The component reliabilities are based on constant failure rates and exponential failure distributions. The overall reliability of the IMU and the major contributors to IMU reliability are computed. Three state-of-the-art fault-tolerant IMU architectures are evaluated and compared using the procedure     

机载机电系统可靠性的计算机辅助分析方法

 为了提高机载机电系统的可靠性,机载机电系统常采用余度系统,以达到故障容错,进而实现整个飞机系统的高可靠性和安全性。开发适应于余度间耦合、动态性能降级的ReliaApp可靠性分析评价软件平台,通过有效综合故障模式影响（FMEA）、故障树分析（FTA）和Markov状态转移链法,实现不同容错设计方案的选择、机电系统的可靠性定量评价并给出系统的薄弱环节,为系统的余度配置和改进设计提供软件设计与评估平台,以确保飞机系统的高可靠性和安全性。实例应用表明该软件平台是飞机机载机电系统可靠性设计与评价有效的计算机辅助工具。     

Digital system design in the presence of single event upsets

The authors consider the effects of single event upsets (SEUs) on digital systems, and show techniques for designing reliable systems with current levels of SEU protection. Three main systems are discussed: main memory, logic, and cache memory. A design for the main and cache memory subsystems that are SEU protected is also described. With SEU defined in bit days p, and using single error correction, it is shown that for all subsystems considered, an effective upset rate which is proportional to the product of p² and the time between corrections, or scrub time, can be obtained. Data for memory chip size and performance derived from the gallium-arsenide (GaAs) pilot lines funded by the Defense Advanced Research Projects Agency (DARPA) throughout the 1980s are used     

A fault-tolerant air data/inertial reference unit

The fault-tolerant air data/inertial reference unit (ADIRU) described is a key part of a fault-tolerant air data/inertial reference system (ADIRS) designed to be the inertial and air data reference for the ARINC 651 Integrated Modular Avionics (IMA) distributed architecture. The ADIRU has been designed to meet the commercial aviation market demands for low life cycle cost and high integrity fault detection, fault isolation, and redundancy management. The ADIRU's internal redundant resources provide quad channel redundancy that is one level higher than conventional triple redundant systems, allowing it to provide deferred maintenance capability. Robust partitioning, simple serial internal interfaces, and simple voting planes ensure that internal redundant components are properly utilized to provide high integrity system outputs. This relieves systems using it from having to perform their own redundancy management of the air data and inertial outputs from multiple sources required by conventional systems     

Fault-Tolerant Encryption for Space Applications

This paper is concerned with the use of commercial security algorithms like the Advanced Encryption Standard (AES) in Earth observation small satellites. The demand to protect the sensitive and valuable data transmitted from satellites to ground has increased and hence the need to use encryption on board. AES, which is a very popular choice in terrestrial communications, is slowly emerging as the preferred option in the aerospace industry including satellites. This paper first addresses the encryption of satellite imaging data using five AES modes—ECB, CBC, CFB, OFB and CTR. A detailed analysis of the effect of single even upsets (SEUs) on imaging data during on-board encryption using different modes of AES is carried out. The impact of faults in the data occurring during transmission to ground due to noisy channels is also discussed and compared for all the five modes of AE?. In order to avoid data corruption due to SEUs, a novel fault-tolerant model of AES is presented, which is based on the Hamming error correction code. A field programmable gate array (FPGA) implementation of the proposed model is carried out and measurements of the power and throughput overhead are presented.     

开放式FADEC系统的数据总线研究

研究了容错数据总线这个从集中式向开放式架构过渡的关键技术.在深入研究确定性、一致性、开放性、拓扑结构、调度策略、容错机制和传输带宽等开放式FADEC(全权限数字电子控制)数据总线关键特征的基础上,分析了总线数据传输的时间不确定性问题.从性能、可靠性和可用性的角度深入研究了TTP/C(time-triggered protocol/automotive class C),ARINC659,TTCAN(time-triggered controller area network)和FlexRay这4种时间触发架构数据总线的关键特征.研究结果表明:TTP/C总线是开放式FADEC的最佳选择,最后提出了一种基于TTP/C总线的航空发动机模块化DEEC(digital electronic engine controller)硬件架构.      

硬件演化理论与应用技术研究

演化硬件具有广阔的应用前景和重大的实用价值,演化硬件通过演化算法可实现自身重构,使系统具有自适应、自组织、自修复的特性。介绍了演化硬件的概念、分类、发展历史及研究现状,讨论了演化硬件的实现思路、存在的难点及其发展趋势。     

A self-healing strategy with fault-cell reutilization of bio-inspired hardware

The self-healing strategy is a key component in designing the bio-inspired embryonics circuit with the structure of cell arrays. However, the existing self-healing strategies of embryonics circuits mainly focus on permanent faults inside the modules of cells such as the function module and the configuration register, while little attention is paid to transient faults. From the point of view of obtaining high efficiency of hardware utilization, it would be a huge waste of hardware resources by permanent elimination when a cell only suffers a transient fault which can be repaired by a configuration mechanism. A new self-healing strategy, the Fault-Cell Reutilization Self-healing Strategy(FCRSS) which presents a method for reusing transient fault cells, is proposed in this paper. The circuit structures of all the modules in the cells are described in detail. In the new strategy, two processes of elimination and reconfiguration are combined. Within the process of fault-cell elimination, cells with transient faults in the embryonics circuit array could be reused simultaneously to replace the functions of the cells on their left side in the same row. Therefore, transient fault-cells in a transparent state can be reconfigured to realize the fault-cell reutilization. Finally,a circuit simulation, resource consumption, a reliability analysis and a detailed normalization analysis are presented. The FCRSS can improve the hardware utilization rate and system reliability at the expense of a small amount of hardware resources and reconfiguration time. Following the conclusion, the method of determining the optimal self-healing strategy is presented according to the environmental conditions.     

Bipartite graph-based control flow checking for COTS-based small satellites

Single event upset(SEU)effect,caused by highly energized particles in aerospace,threatens the reliability and security of small satellites composed of commercial-off-the-shelves(COTS).SEUinduced control flow errors(CFEs)may cause unpredictable behavior or crashes of COTS-based small satellites.This paper proposes a generic software-based control flow checking technique(CFC)and bipartite graph-based control flow checking(BGCFC).To simplify the types of illegal branches,it transforms the conventional control flow graph into the equivalent bipartite graph.It checks the legality of control flow at runtime by comparing a global signature with the expected value and introduces consecutive IDs and bitmaps to reduce the time and memory overhead.Theoretical analysis shows that BGCFC can detect all types of inter-node CFEs with constant time and memory overhead.Practical tests verify the result of theoretical analysis.Compared with previous techniques,BGCFC achieves the highest error detection rate,lower time and memory overhead;the composite result in evaluation factor shows that BGCFC is the most effective one among all these techniques.The results in both theory and practice verify the applicability of BGCFC for COTS-based small satellites.     

基于冷备份多模冗余结构的BRAM自修复方法

随着现场可编程门阵列（FPGA）在空天电子系统中的广泛应用,受空间辐射恶劣环境影响,FPGA中重要的存储器电路BRAM,因采用SRAM技术极易发生位翻转故障,虽绝大部分情况表现为瞬时故障,但永久故障依然存在。针对BRAM自修复方法仅修复瞬时故障的现状,对能同时修复瞬时故障和永久故障的自修复方法进行研究,提出了一种冷备份多模冗余结构,用3个热备份模块和1个冷备份模块来构造BRAM,该结构可通过三模冗余刷新方法修复瞬时故障和冷备份替换方法修复永久故障。给出了整个BRAM自修复系统中各模块的电路结构和实现方法,实验验证了系统的自修复能力,并在可靠性、硬件资源和时间消耗3个方面,通过对比分析论证了自修复方法的有效性。     

余度管理中输入信号的表决策略

为了提高安全可靠性及容错能力,在安全性和可靠性要求较高的系统中,通常会采用冗余设计,双余度即为一种常用的冗余策略。将对双余度计算机管理问题中的输入信号表决策略进行深入研究分析,包括三种表决算法：双通道平均值、双通道加权平均值、双通道和设备的综合,并对它们各自的特点进行了详尽的分析说明。     

嵌入式存储器自修复电路的设计与仿真

介绍了一种存储器自修复电路的仿真设计，其中内建自测试模块中的地址生成器采用LFSR设计，它面积开销相当小，从而大大降低了整个测试电路的硬件开销。而内建自修复模块采用基于一维冗余（冗余行块）结构的修复策略设计。通过16×32比特SRAM自修复电路设计实验验证了此方法的可行性。