电传飞控计算机子系统BIT设计研究

飞控计算机子系统是飞行控制系统的计算和控制核心,影响着飞行安全。采用BIT进行故障检测和定位可以显著提高飞控系统安全性。现阶段的BIT设计研究中,系统级偏向于顶层功能要求的论述,计算设备的BIT研究偏重于通用计算机的软硬件论述,飞控系统向计算机子系统的需求传递和可追溯性不强,也缺乏基于系统工程的飞控计算机子系统BIT设计流程研究。通过对飞控计算机子系统架构的分析得出其通用的组成模块。以此为基础开展BIT设计研究,分析了BIT的分类及特点,提出了BIT设计的通用需求,设计了基于系统工程的飞控计算机子系统BIT设计流程,重点从飞控系统功能需求出发详细论述了飞控计算机子系统BIT的初始化、工作模态转换、测试项目、执行时序及与飞控系统功能高关联度的BIT项目测试的设计方法原理,分析了故障预测及健康管理的设计方法和减少虚警的措施。采用该设计流程和详细设计原理方法的飞控计算机子系统BIT设计通过了地面综合试验的验证。     

基于ATE与BIT组合的NAMP自动测试与故障诊断系统设计

在对机械电气系统状态监控处理机(NAMP)功能、组成、BIT和ATE测试接口等进行测试需求分析基础上,基于ATE系统平台完成了NAMP的自动测试原理和测试流程设计,采用BIT和ATE组合测试技术完成了NAMP的自动测试,采用故障树法完成了NAMP的故障诊断功能。经故障注入实验和使用验证表明,该系统具有测试内容全面,故障定位准确,故障隔离率高等特点。     

某机载设备虚警问题的原因分析及处理方法

分析了外场试飞过程中某机载设备BIT虚警产生的原因及引起的后果,并提出了一套较为全面的BIT虚警解决方案,最后结合实际应用给出了便捷有效的软件算法实例。经过外场试飞验证,该算法大大降低了BIT虚警率,提高了设备的可靠性,并为同类型的机载设备产生的BIT虚警提供了可借鉴的经验。     

BIT综合表示模型研究

 在分析机内测试(BIT)主要设计要素组成的基础上,提出了BIT综合表示模型。建立了BIT综合表示模型的数学定义,包括BIT单元模型、BIT层次关系集合、BIT数据传送方式集合、BIT执行次序集合和BIT综合表示模型。在数学定义的基础上,进一步建立了BIT综合表示的框图模型和表格模型,这两种模型可以直接用于工程分析。最后,以某辅助导航系统为案例,进行了BIT综合表示模型的应用,给出了框图模型结果和表格模型结果,验证了该模型的可用性和有效性。     

机内测试虚警分析和控制

现代飞行器广泛采用机内测试(Built-intest,BIT)技术,以便对其内部故障进行自动检测、诊断和隔离,但是常规BIT面临诊断能力不足和诊断模糊性等问题,导致BIT虚警率高,难以有效发挥其应有的作用.本文论述了BIT虚警的基本理论、虚警的危害及现状,并从BIT虚警产生的原因分析入手,提出了解决虚警问题的一些方法和措施.     

一种基于ROM模型的测试性指标论证方法

针对实践中缺乏理论性、可实施性强的测试性指标论证方法的现状,提出了一种基于可靠度、战备完好率与可维修度（ROM）模型的测试性指标论证方法。从战备完好率（O）、可靠度（R）、可维修度（M）关系式入手,将关系式中的可靠度和可维修度分别用平均故障间隔时间（MTBF）和平均修复时间（MTTR）替换,再建立MTBF和MTTR与故障诊断率、虚警率和机内测试（BIT）故障率的关系式并代入"ROM"关系式,得到战备完好率与测试性指标之间的关系式,建立待解指标与BIT数量之间的关系式,通过代入和消减参数得到战备完好率随BIT数量变化曲线,通过找到曲线极值点得到最佳BIT数量,进而得到最佳的测试性指标。在模型构建和指标求解过程中进行了较为充分的仿真分析,得到了大量与经验相符的规律性结论,为不同对象应用该方法进行参数设置时提供了较为充分的参考。最后应用本文方法对某光电一体化设备进行了指标论证,演示并验证了本文方法的有效性。     

飞行控制计算机模拟接口BIT电路设计及仿真

随着航空电子设备维修性要求的提高以及设备本身要求具备检测隔离故障的能力以缩短维修时间,机内测试(BIT)在测试领域研究中将越来越重要。功能电路BIT系统是航空电子设备整机BIT系统的重要组成部分,因此从解决实际问题出发,针对飞行控制计算机中的模拟输入和输出接口电路,提出了几种BIT的设计方法,并使用Multisim软件对所设计的BIT监测电路进行仿真,仿真结果表明,所设计的BIT电路是可靠及有效的。     

测试性研制阶段数据评估验证方法

分析了现有测试性验证方法应用情况,阐述了测试性研制阶段数据评估验证方法的必要性。通过与现有测试性验证方法的对比分析,提出了一种新的测试性验证方法,并说明了该验证方法的含义和特点。该验证方法可用于故障检测率、故障隔离率和虚警率的验证。建立了该验证方法的工作框架,包括验证要求、验证程序、验证技术和验证组织。重点阐述了该验证方法的两种工作方式实施流程、适用的最小样本量范围、测试性数据收集表格和测试性数据判据。其中,测试性数据收集表格可以记录故障检测、故障隔离和虚警信息。进行了案例应用,给出了数据分析结果和经验总结。案例应用表明该方法能够达到测试性验证的效果。     

机载嵌入式计算机通用化BIT架构设计技术

设计开发了一种通用化BIT软件架构技术,可应用于机载嵌入式计算机.将BIT软件按照功能分为硬件驱动层、测试算法层、测试配置及控制层、应用接口层等,可极大程度实现不同硬件环境、操作系统环境下,BIT软件的可移植性,还定义了一种操作系统启动前实现硬件BIT检测的方法,可有效提高内存、CPU等硬件资源的故障检测率.     

直升机航电系统综合测试设备研制

针对航电系统机载自检系统(BIT)虚警率高、传统测试设备通用性和综合化程度低等问题,设计并实现了某型直升机航电系统综合自动化测试设备,经实际测试验证,此设备各项性能均满足测试需求。     

Role of BIT in support system maintenance and availability

The role of built in test (BIT) in electronic systems has grown in prominence with the advances in system complexity and concern over maintenance lifecycle costs of large systems. In an environment where standards drive system designs (and provide an avenue for focused advancement in technology), standards for BIT are very much in an evolutionary state. The reasons for advancing the effectiveness of BIT include reduced support overhead, greater, confidence in operation, and increased system availability. The cost of supporting military electronic systems (avionics, communications, and weapons systems) has driven much of the development in BIT technology. But what about the systems that support these end items that contain test and measurement instrumentation - such as automatic test equipment (ATE), simulators and avionics development suites? There has also been a beneficial effect on the maintenance and availability of these systems due to the infusion of BIT into their component assemblies. But the effect has been much more sporadic and fragmented. This paper looks at the state of BIT in test and measurement instruments, explain its affect on system readiness, and present ideas on how to improve BIT technologies and standards. This will not provide definitive answers to BIT development questions, since the factors that affect it are specific to the instrument itself. The topics covered in this paper are: definitions of built-in test, instrument BIT history, importance of BIT fault coverage and isolation in support systems, overview of BIT development process issues that limit the effectiveness of BIT Standards related to instrument BIT, making BIT more effective in support system maintenance and availability and conclusions.     

Improving Avionics Fiber Optic Network Reliability & Maintainability

Work is ongoing at NAVAIR to understand how avionics fiber optic BIT technology can help reduce military aviation platform fiber optic network life cycle and total ownership cost. Operational availability enhancements via comprehensive supportability programs combined with keen attentiveness to reliability and maintainability metrics are driving the avionics fiber optic BIT value proposition. Avionics fiber optic BIT technology is expected to reduce failure rate and mean time to repair by predicting link failure before link failure actually occurs, running post-maintenance stress screening upon aircraft start-up, improving fault isolation by reducing the troubleshooting ambiguity zone from three to one, and reducing the need for separate support equipment for system troubleshooting     

Test results judgment method based on BIT faults

Built-in-test(BIT) is responsible for equipment fault detection, so the test data correctness directly influences diagnosis results. Equipment suffers all kinds of environment stresses, such as temperature, vibration, and electromagnetic stress. As embedded testing facility, BIT also suffers from these stresses and the interferences/faults are caused, so that the test course is influenced,resulting in incredible results. Therefore it is necessary to monitor test data and judge test failures.Stress monitor and BIT self-diagnosis would redound to BIT reliability, but the existing antijamming researches are mainly safeguard design and signal process. This paper focuses on test results monitor and BIT equipment(BITE) failure judge, and a series of improved approaches is proposed. Firstly the stress influences on components are illustrated and the effects on the diagnosis results are summarized. Secondly a composite BIT program is proposed with information integration, and a stress monitor program is given. Thirdly, based on the detailed analysis of system faults and forms of BIT results, the test sequence control method is proposed. It assists BITE failure judge and reduces error probability. Finally the validation cases prove that these approaches enhance credibility.     

Evaluation of built-in test

Built-in test (BIT) provides fault finding as a means to aid in system assembly, test, and maintenance. An investigation to evaluate BIT of a particular electronics board used in the in-flight entertainment system for Boeing 777s is described. We found BIT proved useful when failure occurrences were uniquely associated with the operating environment, situations which can result in no-fault found, or could-not duplicate (CND) failures upon test. We also observed cases where the BIT failed to observe failures, and in some cases pointed to the wrong cause of failure. These and other advantages and disadvantages of BIT implementation are discussed     

Flyable fiber-optic radar target generator

Airborne radar relies on Built-in-Test (BIT) for fault detection, fault isolation and system calibration. The capability of BIT is often limited by space, weight, size and cost considerations. Furthermore, the radar does not have a test target that will allow BIT to perform in flight, closed-loop functional test of the complete radar system. This paper describes a fiber-optic based radar test target unit that provides a delayed replica of the transmitted radar signal. The unit will intercept a small amount of radar-transmitted energy, delay it in the fiber, then feed it back into the radar producing a calibrated “echo” at a predetermined radar range. The unit can be installed as part of the airborne radar. The details on the design and testing of a proof-of-concept unit are also given     

Testability evaluation using prior information of multiple sources

Testability plays an important role in improving the readiness and decreasing the lifecycle cost of equipment. Testability demonstration and evaluation is of significance in measuring such testability indexes as fault detection rate（FDR） and fault isolation rate（FIR）, which is useful to the producer in mastering the testability level and improving the testability design, and helpful to the consumer in making purchase decisions. Aiming at the problems with a small sample of testability demonstration test data（TDTD） such as low evaluation confidence and inaccurate result, a testability evaluation method is proposed based on the prior information of multiple sources and Bayes theory. Firstly, the types of prior information are analyzed. The maximum entropy method is applied to the prior information with the mean and interval estimate forms on the testability index to obtain the parameters of prior probability density function（PDF）, and the empirical Bayesian method is used to get the parameters for the prior information with a success-fail form. Then, a parametrical data consistency check method is used to check the compatibility between all the sources of prior information and TDTD. For the prior information to pass the check, the prior credibility is calculated. A mixed prior distribution is formed based on the prior PDFs and the corresponding credibility. The Bayesian posterior distribution model is acquired with the mixed prior distribution and TDTD, based on which the point and interval estimates are calculated.Finally, examples of a flying control system are used to verify the proposed method. The results show that the proposed method is feasible and effective.     

Smart BIT: a plan for intelligent built-in test

A major factor influencing the readiness of today's highly electronics-driven weapons systems is the amount of time spent maintaining them. The attainment of a better understanding of the causes for intermittent and other ill-defined failure modes and development of a greater appreciation for the effect of both external and internal environmental factors on the fault behavior of electronic systems will help to improve the BIT (built-in test) performance. Smart BIT is the name applied to a program of research and development sponsored by Rome Air Development Center (RADC) to investigate, develop, and apply artificial-intelligence (AI) techniques to effect BIT improvement. An overview of that program, its contents and purposes is provided. Deficiencies in current BIT implementations and potential benefits of the Smart BIT program are presented. Components of this approach are discussed and supporting technology areas highlighted. The current plan for implementing this approach is given along with a scenario describing its potential form     

基于时间应力分析的机内测试系统综合降虚警技术

 虚警率高是困扰机内测试（BIT）系统得到广泛应用的主要原因。针对该问题,从机电系统所承受时间应力的角度构建了机内测试系统综合降低虚警技术的总体模型。首先采用双支持向量机（SVM）的方法将实时应力信息与机内测试诊断结果相互关联。在此基础上,提出了基于核主元模糊聚类的虚警识别方法将机电系统多源信息进行综合分析,并通过优化决策实现多级降低机内测试系统虚警的目的。最后,针对某型直升机航空地平仪的机内测试系统进行了试验验证与分析。