带通限幅器对锁相环噪声性能的影响

锁相环路中,在鉴相器前加上AGC（自动增益控制）,可以使环路性能在输入信噪比发生变化时保持稳定,带通限幅器也可以起到类似作用。尽管有一些文章对限幅器的性能作了研究,但是在PLL（锁相环）闭环条件下,鲜有文章分析其对环路噪声性能的影响。因此,文章以基本PLL环路的数学模型为基础,推导出PLL中分别加入相干AGC和带通限幅器后新的环路数学模型,以一阶PLL为例,计算和比较不同控制方式下环路相位误差均方值的变化,最后说明应当根据飞行任务的不同选择对环路更有利的控制方式。     

基于锁相环的光电振荡器频率稳定化研究

通过构建小数分频锁相环,将一个工作于X波段的OEO(OptoElectronic Oscillator,光电振荡器)与OCXO(Oven-Controlled Crystal Oscillator,恒温晶体振荡器)进行锁相,得到了输出信号相位噪声和长期频率稳定度的提升。从PLL(Phase-Locked Loop,锁相环)环路传输特性出发,理论分析了PLL输出信号环路带宽内相位噪声水平和作用范围。为降低OEO整体的相位噪声,采用SIL(Self-Injection-Locking,自注入锁定)使OEO在10Hz~10kHz频偏处的相位噪声得到20dB以上的抑制。在此基础上将此SIL OEO与一个频率为100 MHz的OCXO锁相,获得了频率为9.95GHz、相位噪声为-55dBc/Hz@10Hz和-124dBc/Hz@10kHz的微波信号输出,其频率的重叠阿伦方差在100s平均时间内达到1.14×10~(-11),证明了提出的方案对提升OEO频率稳定性具有一定的实际意义。     

Optimum Acquisition of the Idling First-Order Phase-Locked Loop

Acquisition of the idling first-order phase-locked loop (PLL) is investigated. An analytical solution for the Fokker-Planck equation is found if the noise term is neglected. Furthermore, the modulation signal that optimizes the acquisition is obtained by use of phase-plane techniques and Pontryagin's minimum principle.     

Low C/N_0 Carrier Tracking Loop Based on Optimal Estimation Algorithm in GPS Software Receivers

Suppressing jitter noises in a phase locked loop(PLL) is of great importance in order to keep precise and continuous track of global positioning system(GPS) signals characterized by low carrier-to-noise ratio(C/N0).This article proposes and analyzes an improved Kalman-filter-based PLL to process weak carrier signals in GPS software receivers.After reviewing the optimal-bandwidth-based traditional second-order PLL,a Kalman-filter-based estimation algorithm is implemented for the new PLL by decorrelating the model error noises and the measurement noises.Finally,the efficiency of this new Kalman-filter-based PLL is verified by experimental data.Compared to the traditional second-order PLL,this new PLL is in position to make correct estimation of the carrier phase differences and Doppler shifts with less overshoots and noise disturbances and keeps an effective check on the disturbances out of jitter noises in PLL.The results show that during processing normal signals,this improved PLL reduces the standard deviation from 0.010 69 cycle to 0.007 63 cycle,and for weak signal processing,the phase jitter range and the Doppler shifts can be controlled within ±17° and ±5Hz as against ±25° and ±15 Hz by the traditional PLL.     

高动态下惯性加速度辅助三阶锁相环性能分析

针对高阶跟踪环路稳定性比低阶环路差,大带宽带来测量误差大的问题。研究在高动态环境下,惯导加速度信息辅助卫星接收机三阶载波锁相环跟踪算法,以及不同环路参数下跟踪环路的性能。对载体高动态场景、加速度信息延迟进行建模,并对算法进行了数学仿真。仿真分析结果表明,在加速度信息辅助下,即使压缩载波跟踪环路等效噪声带宽到3Hz,在高达1200g/s的加速度动态下,环路跟踪同样稳定可靠。     

Transient Frequency-Error Statistics in Acquisition of Noiseless First-Order Phase Lock Loop

After a certain time interval from the appearance of a reference signal in a synchronizing system employing a first-order phase lock loop (PLL), the probability that the output frequency error will be higher than a maximum tolerated value is determined. The system is assumed to be noise free.     

Uniform Sampling Analysis of a Hybrid Phase-Locked Loop with a Sample-and-Hold Phase Detector

Phase-locked-loop (PLL) bit synchronizers often employ integrate-and-dump type phase detectors that provide phase error information only at discrete points in time. Usually these phase detectors are followed by sample-and-hold circuits to produce a stairstep error voltage as the input to a standard analog circuit loop filter. When the loop is configured in this manner, it is referred to as a hybrid PLL. Sampled-data analysis methods (Z transforms) are used to determine the stability and transient response of this loop.     

Improved Phase-Locked Loop Performance with Adaptive Phase Comparators

A major problem in phase-locked loop (PLL) design is to meet the requirements of both fast signal acquisition and good synchronous mode performance. This relation is reviewed for different types of phase comparators. As a result a new phase-and-frequency comparator is proposed. This comparator is based on an up-down counter principle and can be considered as an adaptive acquisition control circuit. The analysis of a PLL with the proposed phase comparator is based on an exact calculation method for the pull-in time. It is shown that fast signal acquisition is possible without affecting the filtering properties of the loop. Experimental results are given of the acquisition behavior of a second-order type-2 loop which show a good correspondence with the theoretical analysis.     

Analysis of a Class of Nonlinear Sampled-Data Systems with a Gaussian Input Signal

The problem treated here is the analysis of a class of nonlinear sampled-data systems with a Gaussian input signal. The nonlinear element is a symmetrical limiter (memoryless device) that feeds the linear element. Preceding the limiter is a sampler and zero-order hold unit for data reconstruction. The analysis is predicated on finding an equivalent gain for the nonlinear element such that the mean-square error is a minimum. The nonlinearity is thus replaced by a linear component and the system is then analyzed by conventional techniques. It is also shown that for appropriate sampling rates the sampled-data system is equivalent to a continuous system due to the action of the sampler-hold combination. All calculations pertaining to the limiter input signal require the use of a transfer function that is interior to the feedback loop. However, in developing this transfer function, the overall system is considered so that the system output may be evaluated after the value of equivalent gain has been found.     

Carrier loop architectures for tracking weak GPS signals

The performance of various carrier recovery loop architectures (phase lock loop (PLL), Doppler-aided PLL, frequency lock loop (FLL), and Doppler-aided FLL) in tracking weak GPS signals are analyzed and experimentally validated. The effects of phase or frequency detector design, oscillator quality, coherent averaging time, and external Doppler aiding information on delaying loss of lock are quantified. It is shown that for PLLs the metric of total phase jitter is a reliable metric for assessing low C/N performance of the tracking loop provided the loop bandwidth is not too small (~> 5 Hz). For loop bandwidths that are not too small, total phase jitter accurately predicts carrier-to-noise ratio (C/N) at which loss of lock occurs. This predicted C/N is very close to the C/N predicted by bit error rate (BER). However, unlike BER, total phase jitter can be computed in real-time and an estimator for it is developed and experimentally validated. Total phase jitter is not a replacement for BER, since at low bandwidths it is less accurate than BER in that the receiver loses lock at a higher C/N than predicted by the estimator. Similarly, for FLLs operating at small loop bandwidths, it is found that normalized total frequency jitter is not a reliable metric for assessing loss of lock in weak signal or low C/N conditions. At small loop bandwidths, while total frequency jitter may indicate that a loop is still tracking, the Doppler estimates provided by the FLL will be biased.     

Phase-Lock Loop Jump Phenomenon in the Presence of Two Signals

Jump phenomena are known to exist in many non-linear systems [I], [2], [3]. The non-linear analysis presented in this paper explains and predicts the conditions for the jump phenomenon that is observed in a phase-locked loop (PLL) preceded by an automatic gain control (AGC). The jump phenomenon occurs when the frequency separation AM of two sinusoids at the input to the AGC is greater than the bandwidth B of the linearized PLL. If the loop is initially locked to the stronger signal, the weaker signal will frequency-modulate the PLL voltage-controlled oscillator (VCO) with a modulation frequency AI. The amplitude S2 of the weaker signal al can be increased until it becomes greater than the amplitude Si of the signal being tracked, without causing the loop to lose lock; i. e., the VCO continues to track the original signal. However, if the ratio of the amplitudes S2 S1 = R is increased above some critical value RC > 1, the loop will lose lock on the original signal, and jump to track the interfering signal. If the frequency separation is at least twice the PLL bandwidth, a good approximation for this critical ratio is Rc ? ?w/B.     

基于DDS+PLL的光源调制与功率稳定控制方法CSCD

量子传感器是基于量子操控技术的研究成果,一般具有高精度、小体积等优势。激光器是量子传感器的核心部件,有抽运和检测功能,激光器的稳定性对量子传感器具有重要的意义。提出了一种直接数字合成法(DDS)与锁相回路(PLL)相结合的方法,对激光器进行调制并抑制调制噪声,实现了激光器的稳定输出。基于现有小型量子传感器装置,在DDS生成4kHz参考信号的情况下实现了激光器电流8kHz调制,抑制了调制时调制电流信号噪声约8dB,并提高了激光器输出光功率的稳定性。     

Carrier Tracking by Smoothing Filter Improves Symbol SNR

The potential benefit of using a smoothing filter to estimate a carrier phase over use of phase-locked loops (PLL) is determined. Numerical results are presented for the performance of three possible configurations of an all-digital coherent demodulation receiver. These are residual carrier PLL, sideband-aided residual carrier PLL, and finally sideband aided with Kalman smoother. The average symbol SNR after losses due to carrier phase estimation is computed for different total power SNRs, symbol rates, and symbol SNRs. It is found that smoothing is most beneficial for low symbol SNRs and low symbol rates. Smoothing gains up to 0.7 dB over sideband-aided residual carrier PLL, and the combined benefit of smoothing and sideband aiding relative to residual carrier loop is often in excess of 1 dB.     

Hard Limiter Performance as a Polarity Detector for Extremely Polluted Signals

A hard limiter is a simple, yet highly efficient, RF signal sensor for VLF and LF navigation receivers. The observation reliability is used as the single quality criterion for the hard limiter if applied as a singlebit analog-to-digital converter (ADC). The effects of noise (Gaussian and atmospheric), nonsynchronous and synchronous interference, and dc offset on the observation reliability are described extensively. The single parameter determination Pobs is adequate for characterizing the polarity detector. This facilitates rank ordering of influences disturbing the signal and is a useful tool in optimizing digital tracking loops. The ?built-in? noise-censoring properties of the hard limiter in the presence of atmospheric noise are excellent. Therefore, three different atmospheric noise models are used in the determination of the observation reliability Pobs. Some ways for coping with other disturbances that potentially threaten the good performance of the hard limiter are suggested.     

Effects of Automatic Gain Control on Phase-Locked Loop Behavior in the Presence of Interference

The behavior of a second-order phase-locked loop (PLL) in the presence of an interfering signal has been analyzed by different authors with different results. The discrepancy is attributed to the presence or absence of an automatic gain controlled amplifier preceeding the PLL. Simulation results verify that the presence of the automatic gain controlled amplifier reduces the tendency of the PLL to break lock from the desired signal in favor of the interfering signal     

用于非线性有源天线的耦合锁相环特性分析

为实现非线性有源天线阵波束扫描,研究了互耦锁相环(PLL)的基本特性。通过对互耦PLL的相位动力学方程的稳定性进行分析,建立了具有延时的阵列模型;通过调节环路延时,互耦PLL不同的非线性动力学特性;采用四单元的耦合锁相环阵列实验电路对理论分析进行了验证,从而提出了在设计基于耦合锁相环的非线性有源天线时,必须对环路延时进行控制,防止环路出现振荡和混沌现象。     

Analysis of Squaring Circuit Mechanizations in Costas and Squaring Loops

Two different implementations of the carrier recovery loop for suppressed carrier binary phase-shift keyed (BPSK) signals are considered. In particular, the tracking performance of the squaring loop in which the squaring circuit is mechanized by a limiter/multiplier lier combination to produce the absolute value of the incoming signal, followed by appropriate bandpass filtering, is compared with that of the usual squaring loop whose squaring circuit is the timestwo wo multiplier which exhibits a square law characteristic.     

On Transient and Periodic Signal Detection in Time-Varying Noise Power

Detectability of periodic and synchronously recurrent transient signals in a noisy environment in which the noise power is time varying is investigated. For at least one noise model, it is shown that the basic nonlinearity of the optimum detector is a limiter. Performance of this optimum detector is compared with analog cross-correlation and clipper cross-correlation (CCC) detectors. It is shown that the CCC performs nearly optimally, especially at low signal-to-noise ratios, and that its performance is significantly better than that of the analog cross correlator.     

Noise Performance of a Gated Phase-Locked Loop

The objectives of this paper are two. The first is to show that a gated phase-locked loop (GPLL) is a tracking device whose operation approximates that of a maximum likelihood estimator of the phase of a pulsed sinusoid imbedded in noise. The second is to determine the behavior of theb loop in the presence of noise. It is found that the loop performance is equivalent to that of a continuous phase-locked loop driven by the same noise, plus a continuous sinusoid which has the same power as the pulsed sinusoid at the input of the GPLL.     

Comments on ?M-Ary Cpsk Detection with Noisy Reference and Interiverers?

The effect of cycle slips of the carrier recovery phase-locked loop (PLL) on the performance of coherent M-ary phase-shift keyed (MPSK) systems is dealt with. It is shown that each cycle slip causes a 1 bit error in a differentially encoded and Gray encoded signal stream. Different situations are investigated and compared with regard to the effect of these errors.