基于冷备份多模冗余结构的BRAM自修复方法

随着现场可编程门阵列（FPGA）在空天电子系统中的广泛应用,受空间辐射恶劣环境影响,FPGA中重要的存储器电路BRAM,因采用SRAM技术极易发生位翻转故障,虽绝大部分情况表现为瞬时故障,但永久故障依然存在。针对BRAM自修复方法仅修复瞬时故障的现状,对能同时修复瞬时故障和永久故障的自修复方法进行研究,提出了一种冷备份多模冗余结构,用3个热备份模块和1个冷备份模块来构造BRAM,该结构可通过三模冗余刷新方法修复瞬时故障和冷备份替换方法修复永久故障。给出了整个BRAM自修复系统中各模块的电路结构和实现方法,实验验证了系统的自修复能力,并在可靠性、硬件资源和时间消耗3个方面,通过对比分析论证了自修复方法的有效性。     

对称容错多重处理机的系统结构P件

为了故障检测和瞬时故障屏蔽的目的,提出了混合冗余多重处理机,每个处理机件和每个存(贝宁)模块是三重的。重新配置允许用备件代替失效件,并允许在备件耗尽后库存件重新组合。能容纳任意数目的处理件和存(贝宁)模块。混合冗余总线系统使处理机和存(贝宁)器互连,在那里总线的最初冗余是个设计参数。称为总线管理件(BGU)的舌门电路于许多地方,控制重新配置和测试,从而消除同时发生在一个模块上的失效事件的敏感性。重点应放在动态测试上,这种方法比其它容错计算机系统简单。用语索引——总线分配和转换、数字控制系统,故障检测,容锚计算机、高可系统,混合冗余,多重处理机、系统测试。     

雷达设备中自检电路的原理与应用

本文通过雷达设备中自栓电路的分析，说明了自栓电路在雷达设备中的重要性，帮助维护人员了解自栓电路的原理及应用，便于维护人员尽快排除故障、修复设备。     

基于高速串行总线的电路交换开关模块的设计与实现

电路交换开关模块是新一代航空电子系统中实现数字信号并行处理的关键模块,为数字信号并行处理系统中的各个数据处理模块、信号处理模块提供高速数据传输与交换。从新一代航空电子系统并行处理的发展趋势及需求的角度出发,介绍了电路交换开关模块的设计和实现。电路交换开关模块采用M21131交叉开关构成交换结构,能够快速交换高速信号,支持重配置和重构,能够满足新一代航空电子系统中数字信号并行处理高速率、高可靠性和低延迟等需求。     

基于矩化GO法的某型电动飞机扰流板系统可靠性

扰流板冗余系统提升了新能源电动飞机的可靠性。采用GO法建立电动飞机扰流板系统可靠性模型,设计SIMULINK仿真界面,针对操作符11给出一种新的运算模块。针对扰流板冗余系统设计一种矩化操作符,给出运算流程,有效减少传统GO法在冗余系统建模工作量,利用故障树分析法对结果进行验证。结果表明,本文提出的方法切实可行,为新能源电动飞机扰流板系统可靠性分析提供了新的思路。     

一种对称式双处理器模块的设计与实现

随着嵌入式机载计算机处理任务的增加,系统对数据处理功能模块性能提出了很高的要求,采用对称式双处理器是提高功能模块数据处理能力简单而有效的方法。介绍了对称式双处理器结构特点,提出了模块组成结构以及关键电路的设计实现,给出了模块测试性设计。     

线位移差分传感器检测与自监控电路的设计

针对三余度舵机系统对LVDT调理电路具有自监控功能的要求，提出了一种LVDT自监控信号的检测方法。在此基础上，运用时分复用技术，设计了采用一片LVDT信号调节芯片同时检测输出LVDT位移量信号和LVDT故障监控信号的调理电路。并对电路的线性度和故障检测能力进行了实验和分析。     

集总化航空电子系统的可靠性设计

集总化航空电子系统全面考虑了飞机整体性能要求，综合提供了现代飞机所必需的各种信息处理和计算功能。在集总化电子系统设计中，采用多重模块的并－串联冗余结构布局，设置多重冗余的输入、输出交连总线，保持系统各功能模块之间的隔离性等措施以提高系统的可靠性。     

通用指挥仪电路板检修设备的设计

针对指挥仪电路板的特点,介绍了以指挥仪电路板维护为背景的检修设备的硬件和软件设计.着重论述了信号发生器模块电路的设计思路并采用Lab Windows/CVI开发平台进行了测试软件的设计.     

基于VHDL的Viterbi译码器的实现

介绍了一种运用VHDL来实现维特(Viterbi)译码器的方法。详细描述了维特比译码器的优化算法和用VHDL语言实现原理。电路在集成开发环境MAX PLUSII下可以完成设计、仿真、适配并下载。文中给出了维特比译码器顶层设计电路图，以及电路的主要模块和总体电路的仿真结果。其仿真结果表明，用VHDL实现维特比译码器是一种快速有效的方法。     

Efficient approaches to low-cost high-fault coverage VLSI BISTdesigns

This work introduces a built-in self-test (BIST) design methodology that can sequentially test large very large scale integrated (VLSI) circuits with very high fault coverage. The proposed techniques, circular BIST ((BIST) and (BIST with pseudopartial scan (PPSCAN), are modeled after the principles of the circular self-test path (CSTP). The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It is shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared with existing sequential test methods. The effectiveness of the technique has been demonstrated by applying it to practical VLSI circuits, which include: 1) the system control coprocessor (CP0) of MIPS 3000 central processing unit (CPU) core and 2) the SIMD graphic engine, namely, enhanced memory chip (EMC). The BIST results show that (BIST and its derivative (BIST with pseudopartial scan (PPSCAN) are feasible for practical VLSI designs and generate BIST with high fault coverage and low overhead     

Digital Computation Makes AFCS More Reliable

In airline service the reliability of a system is more than the confirmed failures for the system; it is the total removal experience of the system. Thus, the reliability of a system lies not only in the piece part failure rates, but also in the capability to verify and isolate failures. The application of digital technology brings several significant reliability improvements to automatic flight control systems (AFCS) when compared to contemporary analog systems. These advantages are demonstrated by the experience of the digital air data computer (DADC) of the DC-10 and the digital AFCS of the JA-37 Viggen. Experience with this equipment is reviewed, and the results are interpreted in terms of projections for airline DAFCS reliability. The digital system built-in test implemented by a stored program and the central processor gives a system integrity and dispatch reliability unequaled by analog systems. This high-integrity self-test reduces removal rates by giving line personnel a trustworthy tool and more complete automatic test processes for verifying maintenance actions. Digital circuit technology is directly suitable to largescale integrated circuits (LSIC) which reduce piece part counts and improve LRU reliability. Digital circuits are less subject to drift and the attendant difficulty to detect failures. These factors, coupled with the inherent high-integrity self-test, provide the basis for a significant improvement in reliability by the use of a digital automatic flight control system.     

九开关变换器驱动六相电机的载波调制PWM控制

针对九开关变换器驱动六相永磁同步电机系统的断相运行状态,研究了一种基于有效作用时间的载波调制PWM控制方法。给出了九开关变换器及基于有效作用时间的载波调制PWM控制的基本原理,建立了正常情况下六相PMSM的数学模型,根据单相和两相断路后电机相应的约束条件,采用空间解耦变换矩阵,分别建立了单相断路和两相断路后的电机数学模型,在Matlab/Simulink中进行了仿真实验,验证了所提控制方法的可行性。     

三相高频斩波式AC/AC变换器控制电路的分析与设计

分析与设计基于一种实用的三相高频斩波式AC／AC变换器的研制,以高频脉宽调制(PWM)技术取代了传统的基频电压补偿技术,不仅减小了体积和重量,且提高了效率和响应速度。主要对控制电路进行了分析与设计,其中包括输出采样电路、闭环反馈电路以及驱动电路;并对控制电路的稳定性进行了分析,给出了系统框图、传递函数以及波特图。在分析与设计中,通过稳定RMS值实现输出电压的稳定;采用有源滤波技术,减小了控制电路中的高次谐波干扰;利用齐纳二极管正温度特性,减小了系统的温度漂移,较好地补偿了采样电路中整流二极管的负温度特性;采用可编程调节死区的驱动电路,完全满足三相斩波式AC／AC变换器四路驱动信号的电器隔离和时序要求。     

Multi-objective evolutionary design of selective triple modular redundancy systems against SEUs

To improve the reliability of spaceborne electronic systems,a fault-tolerant strategy of selective triple modular redundancy(STMR)based on multi-objective optimization and evolvable hardware(EHW)against single-event upsets(SEUs)for circuits implemented on field programmable gate arrays(FPGAs)based on static random access memory(SRAM)is presented in this paper.Various topologies of circuit with the same functionality are evolved using EHW firstly.Then the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it,and each circuit is hardened against SEUs by selectively applying triple modular redundancy(TMR)to these SEU-sensitive gates.Afterward,each circuit hardened has been evaluated by SEU Simulation,and the multi-objective optimization technology is introduced to optimize the area overhead and the number of functional errors of all the circuits.The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of North Carolina(MCNC)benchmark suite.The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability.The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58%with the same SEU immunity.     

用活性碳毡制备电路模拟吸波材料的研究

研究了以粘胶基活性碳纤维为导电材料制备单层电路模拟吸波材料的微波吸收特性。结果表明：感性电路屏在毡条宽为5mm、α／b为2时吸波性能最好，在8GHz～18GHz内达到-10dB以下的反射衰减，最大衰减峰达一30dB以上；容性电路屏在毡块间距为5mm、α／b为1．4时吸波性能最好，在8GHz～18GHz内达到-10dB以下的反射衰减，最大衰减峰值-30dB以上。可用粘胶基活性碳毡制备质轻价廉的雷达吸波材料。     

Capacity as a consideration for providing aeronautical mobilesatellite air traffic services in the US domestic airspace

A preliminary analysis of the capacity (number of aircraft) that could be handled by the first generation American Mobile Satellite Corporation (AMSC) system in the early part of the 21st century is reported. The analysis is based on assumptions for the service demand, the Aeronautical Telecommunication Network (ATN), the communications scheme, the satellite channel and the aircraft Earth station. Capacity is examined in terms of spectral bandwidth required and satellite power limitations. The sensitivity of the results is examined with regard to variations in service demand; spectral efficiencies of different modulation techniques; aircraft antenna equipage, high-gain or low-gain; and the amount of overhead associated with the ATN. With regard to the ATN, the analysis only illustrates the impact on capacity if some of the ATN overhead were eliminated. The feasibility of eliminating this overhead and the possible resulting loss of functionality are not addressed     

VXI based breadboard module use

Plug-in VXI based breadboard modules are an excellent solution to achieve a lower costing, time and hardware saving test bench. These breadboard modules are equipped with built-in VXI bus interface circuitry and a breadboard area for creating a design to suit your test needs. A prime example for the use of this capability was demonstrated on a recent radar system test bench created to test many unique Units Under Test (UUTs) previously tested on separate test benches. A single breadboard module design replaced the dedicated interface and control hardware within the many test benches and test fixtures previously used to test the individual UUTs. This paper presents some design considerations and techniques implemented as part of this VXI breadboard module that can be useful when creating a VXI breadboard design. It also addresses the inherent built-in test capabilities provided by the module in conjunction with the techniques presented in the paper     

Integrating Voice and Data on Circuit-Switched Networks

Integrating voice and data traffic on a common network using circuit switching is considered. A reasonable design methodology was employed to probe a variety of economic issues. Among these were the cost benefits of voice digitization, the effect of data terminal user behavior, and the overhead of network signaling.     

绝对式恒光源24位光电轴角编码器在光电经纬仪上的应用

为满足某型光电经纬仪的使用要求,设计了某绝对式恒光源 24位光电轴角编码器分系统。该编码器采用 16位绝对式光学码盘,码盘刻划有粗码道、通圈码道、中精码道和精码道。精码道的线对数为 16 384(14位)。方位和高低编码器的处理电路设计在一块电路板上,采用一片 DSP为主机,6个读数头输出 64路码盘光电信号分别经放大整形、A/D转换输入至 DSP。DSP完成数据采集、细分、译码、校正等处理,把轴的转角变换成 24位自然二进制角度代码输出和上传。使用情况表明:该编码器的光机结构布局合理、性能稳定,电路板和元器件少、操作简单、测角精度高,满足某型光电经纬仪对于编码器系统的要求,具有较高的实用价值。