Interferences in Phase-Locked Loops

An analysis of the behavior of a second-order phase-locked loop is presented when an unwanted signal is added to the useful signal. Both signals are sinusoidal and unmodulated, and the analysis is made in the absence of additive noise. When the loop remains locked on the useful signal, a parasitic signal exists at the phase detector output. This signal produces a parasitic phase modulation of the VCO and a static phase error in the loop. The parasitic signal amplitude, the parasitic phase modulation index, and the static phase error are calculated. A necessary condition for the loop to remain in lock is derived. When the loop is initially unlocked, locking can occur either on the useful signal or on the unwanted signal, depending on the amplitude ratio and the frequency difference of the two signals. A formula allowing one to compute the pull-in time is obtained. When the loop locks on the useful signal, acquisition can be slower or faster than in the absence of an unwanted signal. The same phenomenon is observed when the loop locks on the unwanted signal.     

Implementation of a three-phase high-power-factor rectifier with NPC topology

A three-phase four-wire power factor corrector based on neutral-point-clamped (NPC) topology is adopted to reduce the current harmonics and increase the input power factor. Using the NPC topology, the voltage stress of power switches can be reduced to the half of the dc-link voltage. With the dc-link voltage controller and the phase locked loop circuit, the balanced and sinusoidal line currents can be drawn from the ac supply system under the balance and unbalance mains voltages. The hysteresis current comparators are adopted in the current control loop to track the line current commands. Three voltage levels are generated on the ac terminal to the neutral point. Simulations and experiments are provided to verify the validity and the effectiveness of the proposed control scheme.     

基于MC145152的VOR地面信标模仿仪频率合成器的设计与实现

提出了VOR地面信标模仿仪对频率合成器的要求,介绍了集成锁相环芯片MC145152的工作特性,验证了基于MC145152的PLL频率合成器在VOR地面信标模仿仪中的设计与实现的有效性。测试结果证明设计的合理性与实用性,系统频率稳定度优于10-7。     

Carrier loop architectures for tracking weak GPS signals

The performance of various carrier recovery loop architectures (phase lock loop (PLL), Doppler-aided PLL, frequency lock loop (FLL), and Doppler-aided FLL) in tracking weak GPS signals are analyzed and experimentally validated. The effects of phase or frequency detector design, oscillator quality, coherent averaging time, and external Doppler aiding information on delaying loss of lock are quantified. It is shown that for PLLs the metric of total phase jitter is a reliable metric for assessing low C/N performance of the tracking loop provided the loop bandwidth is not too small (~> 5 Hz). For loop bandwidths that are not too small, total phase jitter accurately predicts carrier-to-noise ratio (C/N) at which loss of lock occurs. This predicted C/N is very close to the C/N predicted by bit error rate (BER). However, unlike BER, total phase jitter can be computed in real-time and an estimator for it is developed and experimentally validated. Total phase jitter is not a replacement for BER, since at low bandwidths it is less accurate than BER in that the receiver loses lock at a higher C/N than predicted by the estimator. Similarly, for FLLs operating at small loop bandwidths, it is found that normalized total frequency jitter is not a reliable metric for assessing loss of lock in weak signal or low C/N conditions. At small loop bandwidths, while total frequency jitter may indicate that a loop is still tracking, the Doppler estimates provided by the FLL will be biased.     

基于UKF准开环结构的高动态载波跟踪环路

 对高动态环境下的全球卫星导航系统（GNSS）载波信号跟踪方法进行了研究。在分析高动态载波信号模型的基础上,提出了一种基于无迹卡尔曼滤波（UKF）的准开环载波跟踪方法。此方法能够消除导航数据二进制相移键控(BPSK)调制的影响,并采用四维UKF相位估计模型提高跟踪精度,同时对估计值进行补偿以减少滤波器的滞后性。通过模拟接收机的高动态运动轨迹,从跟踪误差、跟踪结果和补偿效果3个方面,与基于卡尔曼滤波（KF）的锁频环(FLL)辅助锁相环(PLL)结构的传统跟踪方法进行比较,结果表明基于UKF的准开环跟踪方法能够有效地完成高动态环境下的载波跟踪。     

基于鉴相器的矢量跟踪环设计

基于鉴相器的矢量跟踪环是锁定导航卫星码和载波的一种跟踪算法,这种算法适合于在弱信号环境下进行跟踪。矢量环不仅充分利用信号跟踪和导航状态解算之间的内在耦合关系,而且每一通道中采用鉴相器和锁频环结合的方式,系统一步内完成信号跟踪和导航解算任务。反馈控制量NCO是由导航滤波器和环路内部滤波器共同产生。实验表明,矢量跟踪环具有快速重捕获特性,能够在弱信号的环境下运行,比起传统环路有更小的跟踪误差。     

用于非线性有源天线的耦合锁相环特性分析

为实现非线性有源天线阵波束扫描,研究了互耦锁相环(PLL)的基本特性。通过对互耦PLL的相位动力学方程的稳定性进行分析,建立了具有延时的阵列模型;通过调节环路延时,互耦PLL不同的非线性动力学特性;采用四单元的耦合锁相环阵列实验电路对理论分析进行了验证,从而提出了在设计基于耦合锁相环的非线性有源天线时,必须对环路延时进行控制,防止环路出现振荡和混沌现象。     

基于MC145152的VOR地面信标模仿仪频率合成器的设计与实现

本文提出了VOR地面信标模仿仪对频率合成器的要求,介绍了集成锁相环芯片MC145152的工作特性,验证了基于MC145152的PLL频率合成器在VOR地面信标模仿仪中的设计与实现的有效性。     

基于锁相环的光电振荡器频率稳定化研究

通过构建小数分频锁相环,将一个工作于X波段的OEO(OptoElectronic Oscillator,光电振荡器)与OCXO(Oven-Controlled Crystal Oscillator,恒温晶体振荡器)进行锁相,得到了输出信号相位噪声和长期频率稳定度的提升。从PLL(Phase-Locked Loop,锁相环)环路传输特性出发,理论分析了PLL输出信号环路带宽内相位噪声水平和作用范围。为降低OEO整体的相位噪声,采用SIL(Self-Injection-Locking,自注入锁定)使OEO在10Hz~10kHz频偏处的相位噪声得到20dB以上的抑制。在此基础上将此SIL OEO与一个频率为100 MHz的OCXO锁相,获得了频率为9.95GHz、相位噪声为-55dBc/Hz@10Hz和-124dBc/Hz@10kHz的微波信号输出,其频率的重叠阿伦方差在100s平均时间内达到1.14×10~(-11),证明了提出的方案对提升OEO频率稳定性具有一定的实际意义。     

Phase-Lock Loop Jump Phenomenon in the Presence of Two Signals

Jump phenomena are known to exist in many non-linear systems [I], [2], [3]. The non-linear analysis presented in this paper explains and predicts the conditions for the jump phenomenon that is observed in a phase-locked loop (PLL) preceded by an automatic gain control (AGC). The jump phenomenon occurs when the frequency separation AM of two sinusoids at the input to the AGC is greater than the bandwidth B of the linearized PLL. If the loop is initially locked to the stronger signal, the weaker signal will frequency-modulate the PLL voltage-controlled oscillator (VCO) with a modulation frequency AI. The amplitude S2 of the weaker signal al can be increased until it becomes greater than the amplitude Si of the signal being tracked, without causing the loop to lose lock; i. e., the VCO continues to track the original signal. However, if the ratio of the amplitudes S2 S1 = R is increased above some critical value RC > 1, the loop will lose lock on the original signal, and jump to track the interfering signal. If the frequency separation is at least twice the PLL bandwidth, a good approximation for this critical ratio is Rc ? ?w/B.     

Improved Phase-Locked Loop Performance with Adaptive Phase Comparators

A major problem in phase-locked loop (PLL) design is to meet the requirements of both fast signal acquisition and good synchronous mode performance. This relation is reviewed for different types of phase comparators. As a result a new phase-and-frequency comparator is proposed. This comparator is based on an up-down counter principle and can be considered as an adaptive acquisition control circuit. The analysis of a PLL with the proposed phase comparator is based on an exact calculation method for the pull-in time. It is shown that fast signal acquisition is possible without affecting the filtering properties of the loop. Experimental results are given of the acquisition behavior of a second-order type-2 loop which show a good correspondence with the theoretical analysis.     

基于DDS+PLL的光源调制与功率稳定控制方法CSCD

量子传感器是基于量子操控技术的研究成果,一般具有高精度、小体积等优势。激光器是量子传感器的核心部件,有抽运和检测功能,激光器的稳定性对量子传感器具有重要的意义。提出了一种直接数字合成法(DDS)与锁相回路(PLL)相结合的方法,对激光器进行调制并抑制调制噪声,实现了激光器的稳定输出。基于现有小型量子传感器装置,在DDS生成4kHz参考信号的情况下实现了激光器电流8kHz调制,抑制了调制时调制电流信号噪声约8dB,并提高了激光器输出光功率的稳定性。     

平台系统数字化框架轴锁定回路设计

平台系统测试设备要求平台在不开盖条件下实现框架锁定,在对陀螺和加速度计进行多位置测试时,必须确保平台框架处于正交锁定状态。原平台系统锁定回路是由模拟电路搭建,不但存在框架抖动问题,而且只能利用机械锁进行框架锁定。针对上述缺陷,本文对原模拟锁定回路进行了数字化改进设计,利用DSP实现传感器信号滤波、控制算法及PWM波输出,再经过功率驱动后控制各框架轴力矩电机实现框架锁定。经仿真和试验验证,数字化锁定回路性能满足测试设备对锁定回路技术要求。     

Phase Locked Loop Acquisition for a Noisy FM Signal

A method based upon the quasi-linearization technique of evaluating the pull-in characteristics of a phase locked loop for an angle modulated signal corrupted with Gaussian noise is presented. Experimental results along with formulas for calculating the locking range and locking time are also presented and they are in good agreement with the theoretical results. Some new findings regarding the dependence of the locking range and locking time on the modulating frequency are also incorporated.     

三相高频斩波式AC/AC变换器控制电路的分析与设计

分析与设计基于一种实用的三相高频斩波式AC／AC变换器的研制,以高频脉宽调制(PWM)技术取代了传统的基频电压补偿技术,不仅减小了体积和重量,且提高了效率和响应速度。主要对控制电路进行了分析与设计,其中包括输出采样电路、闭环反馈电路以及驱动电路;并对控制电路的稳定性进行了分析,给出了系统框图、传递函数以及波特图。在分析与设计中,通过稳定RMS值实现输出电压的稳定;采用有源滤波技术,减小了控制电路中的高次谐波干扰;利用齐纳二极管正温度特性,减小了系统的温度漂移,较好地补偿了采样电路中整流二极管的负温度特性;采用可编程调节死区的驱动电路,完全满足三相斩波式AC／AC变换器四路驱动信号的电器隔离和时序要求。     

基于FPGA的硅微机械陀螺仪数字化驱动电路研究

为了进一步提高硅微机械陀螺仪的性能,提出了一种基于FPGA数字信号处理来实现控制的数字化驱动电路。该设计方案通过AGC环路稳定了驱动幅度,并用SPLL对相位进行了控制以跟踪谐振频率。两主要环路以FPGA为硬件基础,用软件编程实现,相较模拟驱动电路在实际应用中更具灵活性。实验给出了该电路的驱动幅度和频率漂移曲线,证明了该电路可以较好的实现硅微机械陀螺仪的驱动。     

Digital Frequency-Lock Generator

A digital frequency-lock generator has been developed which produces an output pulse train automatically locked to the pulse repetition rate, or frequency, of an input pulse train. This device, which exhibits a wide capture range and has no static output frequency drift, offers several advantages over a phase-lock loop in frequency-locking applications.     

基于反馈的振荡器注频锁相研究

注频锁相技术是非线性有源阵列天线的关键技术之一,论文提出了一种带反馈的振荡器注频锁相闭环结构。与开环结构相比,该电路能够提高锁频带宽,可用来构成非线性有源天线阵。仿真结果表明该电路相噪低,具有更宽的锁相带宽。     

基于DSC整流器和双闭环PR逆变器的模块化中频静变电源

与传统中频电源相比,模块化中频静变电源具有选用灵活、可靠性高、冗余性好、便于系统维护等优点。中频静变电源整流器在控制母线电压稳定的同时还要实现单位功率因数控制。为此,具体分析了双电流环控制策略,给出了双电流环控制器中电压电流正负序分离原理和双dq锁相环的具体实现方法,即延时信号抵消(DSC)和双闭环准比例谐振(PR)。针对逆变器输出电压基波无差跟踪困难、谐波含量高等问题,采用双闭环多重准PR控制策略,实现中频电压的稳定输出。仿真和试验结果表明,双电流环控制器能同时实现母线电压稳定和单位功率因数控制,采用双闭环多重准PR控制策略的中频逆变器能够输出稳定的中频交流电压。     

一种永磁同步电机宽速域无传感器系统的控制策略

设计了一种改进型滑模观测器(SMO)实现永磁同步电机(PMSM)无传感器宽速域控制。使用反电动势观测器替代低通滤波器,避免了转子位置信息滞后的问题。在定子电流计算中引入随转速自适应调节反馈系数的反电动势反馈,减小了系统抖振,使宽速域下转子转速和位置估计更加精确。采用锁相环技术(PLL)来抑制高频信息,提取出准确的转子位置。基于dSPACE搭建了PMSM的快速控制原型试验平台,对无传感器控制系统进行了稳态和动态试验,结果验证了该算法的有效性。