一种供电特性试验设备的实现方法

随着航空电子技术的发展,实现对航空电子设备供电特性的自动化检测就变得日益重要。介绍了一种在实验室环境下实现供电特性试验自动化测试的方法。根据国内外现行的相关测试标准对机载电子设备的供电特性测试要求,以及实验室原有电源测试设备,从硬件结构和软件程序两方面进行了分析;并进行硬件改造、软件升级,设计了输出管理部件、增加了高精度可控源、更改了部分测试程序,实现了输入浪涌、输入瞬变等测试功能,从而完成机载电子设备的供电特性试验。     

飞行控制计算机模拟接口BIT电路设计及仿真

随着航空电子设备维修性要求的提高以及设备本身要求具备检测隔离故障的能力以缩短维修时间,机内测试(BIT)在测试领域研究中将越来越重要。功能电路BIT系统是航空电子设备整机BIT系统的重要组成部分,因此从解决实际问题出发,针对飞行控制计算机中的模拟输入和输出接口电路,提出了几种BIT的设计方法,并使用Multisim软件对所设计的BIT监测电路进行仿真,仿真结果表明,所设计的BIT电路是可靠及有效的。     

ARINC 653─实现软件重用

软件重用模块电子ARINC653（APEX）规范的主要目标,是通过为应用软件提供标准的操作环境来实现软件重用。软件重用可由两种方式实现：①由重用操作系统,该系统通过应用频谱提供一些通用功能,如健康监控、过程管理、通信原理;②由重用提供航空电子应用功能的应用软件。通过在应用和操作系统之间提供标准的接口,ARINC653促进这两种形式的重用。由于操作系统与基础硬件平台自然紧密地连接在一起,所以操作系统的重用限制了应用相同硬件的模块,除非能严格地确定一种象COEX（核执行接口）这样的新型标准。应用软件通常取决于实际的…     

便携式飞机电缆智能检测系统设计

介绍了一种便携式智能型飞机电缆性能检测系统,给出了系统的硬件电路和软件流程,实现了对飞机各机载系统线路故障的现场分析和测试。     

通用无人机仿整机自动测试系统设计与实现

如何高效而精确的检测无人机机载设备的功能与性能,越来越重要且急迫。文章提出了一种将无人机机载计算机作为自动测试系统组成部分,并利用测试资源模拟无人机机载设备输入输出信号,仿真机载设备功能的测试系统设计方法,充分发挥机载计算机本身与其他机载设备的数据交联功能,以保持测试系统与实际装备工作环境一致,使得无人机整机BIT和正常工作过程能顺利完成。通过配备不同型号无人机的机载计算机和测试附件,可完成多型号无人机的测试,有效提高了内场检测维修的能力,提升了无人机的战斗力。     

温室环境无线传感器节点设计

针对目前国内温室环境参数有线监测系统的不足,设计了一种温室环境无线传感器节点。节点硬件以Mica2节点为核心,使用SHT11传感器测量室内温度和相对湿度,使用TSL2561传感器测量室内光照度。节点工作频段433MHz,比2.4GHz频段的无线传感器节点具有更好的绕射传输能力。节点软件设计采用TinyOS操作系统,用软件看门狗提高节点的抗干扰能力,通过ACK传输机制提高无线通信质量。测试结果表明,该节点运行较稳定,可用于温室环境实时监测。     

基于虚拟仪器的航空直流电源系统电气参数测试

为了实现对航空直流电源的快速检测,提出了一种基于虚拟仪器的航空直流电源系统电气参数测试的设计方案,阐述了测试系统的硬件组成和测试系统软件模块。测试系统软件采用LabVIEW软件开发平台,主要由数据采集软件和数据处理软件两部分组成。实际应用表明,各项测试指标均达到了设计要求,系统具有运行稳定可靠、操作方便、维护简单的特点,能够满足航空直流电源的测试需要。     

SDES：一种卫星入轨故障诊断专家系统原型

文章探讨利用专家系统技术和汉语语音合成技术等,实现航天器智能测试诊断的问题,介绍以此为目的开发的一种卫星入轨故障诊断专家系统原型,和实现这种原型过程中的主要工作,如问题择选、硬软件工具选择、硬件环境设计、软件环境设计、知识获取、系统结构设计、系统实现、存在问题分析与发展考虑等等。     

某型军机军械火控系统自动测试仪的设计与研究

传统的机载火控系统性能测试技术含量低,不能满足现代战争的需要.为提高部队的快速反应能力,研制了一种基于VXI总线技术组建的机载火控系统自动测试,并给出了测试仪的硬件配置和在Lab Windows/CVI环境下的软件模块化设计方案及实现方法.机载火控系统自动测试仪的研制,为部队战时或训练现场实时测试机载火控系统的主要性能提供了方便.     

NAMP系统虚警问题分析研究

随着计算机技术和微电子技术的迅艋发展,如机载雷达、飞控系统等航空电子系统可利用自身的机载计算机进行机内测试(BIT).但如液压系统,起落架系统等非航空电子系统本身没有计算机,无法对自身的故障进行检测、诊断和隔离.     

An Approach to Built-In Testing

The archiitecture and justification for an approach to built-in testing (BIT) in electronic circuits and systems is presented. The proposed system is capable of on-line fault detection and prediction up to the shop replaceable assembly (SRA) level and is designed to interface with external automatic test equipment (ATE) for off-line fault diagnosis within the SRA. The constituent parts of the BIT system have been extensively simulated and the approach appears to be suitable for hardware implementation both with respect to computational and economic considerations.     

Instrumenting embedded test software in support system integration, factory production, and depot repair

Embedded built-in test (BIT) software typically provides a system-level go/no-go indication and, in the presence of a failure, may provide some level of sub-system isolation. This level of reporting, while meeting the customer's operational requirements, does little to support system integration, production, and repair. To support these other needs, "instrumentation code" is added to the BIT software to provide detailed test data through an external interface. Since the BIT software already accesses the hardware parameters for testing, it becomes the most logical component for the instrumentation. This paper describes the techniques of embedding instrumentation during BIT design and development to support a broad range of program test needs. It explains the costs and benefits associated with the use of instrumentation. It gives specific examples of instrumented software and describes how instrumentation data can be used during environmental tests, factory test, and depot test. The impact instrumentation has on software development time, code size, execution time, and reliability is discussed as well as the cost of retrofitting BIT software to add instrumentation. Some of the benefits as well as the challenges to developing effective embedded instrumentation is also examined.     

Analysis tools for the evaluation of maintenance software

Test packages written for built-in test (BIT) and mobile automatic test equipment (ATE) systems for the forward support of electronic and thermal imaging equipment used by the British Army are currently scrutinized and subjected to objective tests by test package evaluation and acceptance teams (TPEATs) before being accepted for field use. This is a time-consuming and costly exercise that can result in the rejection of unsuitable software. The result of such rejection on equipment logistics is for reaching, since the hardware will enter service without adequate maintenance support. In an attempt to address this problem a suite of programs aimed at assisting the verification and validation activities of the TPEAT at every stage of the software life cycle from requirements analysis through to testing and acceptance is being devised. The development of these tools is discussed     

An attack-immune trusted architecture for supervisory aircraft hardware

With the wide application of electronic hardware in aircraft such as air-to-ground communication, satellite communication, positioning system and so on, aircraft hardware is facing great secure pressure. Focusing on the secure problem of aircraft hardware, this paper proposes a supervisory control architecture based on secure System-on-a-Chip (SoC) system. The proposed architecture is attack-immune and trustworthy, which can support trusted escrow application and Dynamic Integrity Measurement (DIM) without interference. This architecture is characterized by a Trusted Monitoring System (TMS) hardware isolated from the Main Processor System (MPS), a secure access channel from TMS to the running memory of the MPS, and the channel is unidirectional. Based on this architecture, the DIM program running on TMS is used to measure and call the Lightweight Measurement Agent (LMA) program running on MPS. By this method, the Operating System (OS) kernel, key software and data of the MPS can be dynamically measured without disturbance, which makes it difficult for adversaries to attack through software. Besides, this architecture has been fully verified on FPGA prototype system. Compared with the existing systems, our architecture achieves higher security and is more efficient on DIM, which can fully supervise the running of application and aircraft hardware OS.     

Flyable fiber-optic radar target generator

Airborne radar relies on Built-in-Test (BIT) for fault detection, fault isolation and system calibration. The capability of BIT is often limited by space, weight, size and cost considerations. Furthermore, the radar does not have a test target that will allow BIT to perform in flight, closed-loop functional test of the complete radar system. This paper describes a fiber-optic based radar test target unit that provides a delayed replica of the transmitted radar signal. The unit will intercept a small amount of radar-transmitted energy, delay it in the fiber, then feed it back into the radar producing a calibrated “echo” at a predetermined radar range. The unit can be installed as part of the airborne radar. The details on the design and testing of a proof-of-concept unit are also given     

CSDB协议及其总线信号的测试

介绍了广泛应用于现代民用客机上的商业标准数字总线（CSDB）协议，并重点分析了CSDB总线信号测试的硬件结构和软件设计，测试设备基于PC104工业控制平台，可作为飞机外厂维修的便携式测试仪器。     

机内测试虚警分析和控制

现代飞行器广泛采用机内测试(Built-intest,BIT)技术,以便对其内部故障进行自动检测、诊断和隔离,但是常规BIT面临诊断能力不足和诊断模糊性等问题,导致BIT虚警率高,难以有效发挥其应有的作用.本文论述了BIT虚警的基本理论、虚警的危害及现状,并从BIT虚警产生的原因分析入手,提出了解决虚警问题的一些方法和措施.     

光学测量中心站远程监控系统实现

为了在执行航天任务时,远程控制数台光学测量设备对飞弹轨道的精密测量,设计了光学测量设备远程控制中心站。远程控制中心站的硬件系统完成计算机与各外置板卡间的通信,计算机使用带中断支持功能的I/O卡连接B码时统设备辨识出硬件信号;而软件系统则使用核心框架与业务逻辑层分离的方法进行设计。其中,核心框架层完成与所有接入系统的硬件传感器的通信及Windows内核级对象管理功能、中断服务功能、数据文件存储功能,核心框架只有很少的界面;业务逻辑层完成界面展现与数据处理功能,是具体的项目逻辑部分。核心框架与业务逻辑之间使用公用缓冲区与消息机制进行通信,这样,一旦软件系统的核心框架层调试完成后,将可用于更多相似的工程项目。通过分析,光学测量设备远程控制中心站可以实现全自动无人值守。     

Test results judgment method based on BIT faults

Built-in-test(BIT) is responsible for equipment fault detection, so the test data correctness directly influences diagnosis results. Equipment suffers all kinds of environment stresses, such as temperature, vibration, and electromagnetic stress. As embedded testing facility, BIT also suffers from these stresses and the interferences/faults are caused, so that the test course is influenced,resulting in incredible results. Therefore it is necessary to monitor test data and judge test failures.Stress monitor and BIT self-diagnosis would redound to BIT reliability, but the existing antijamming researches are mainly safeguard design and signal process. This paper focuses on test results monitor and BIT equipment(BITE) failure judge, and a series of improved approaches is proposed. Firstly the stress influences on components are illustrated and the effects on the diagnosis results are summarized. Secondly a composite BIT program is proposed with information integration, and a stress monitor program is given. Thirdly, based on the detailed analysis of system faults and forms of BIT results, the test sequence control method is proposed. It assists BITE failure judge and reduces error probability. Finally the validation cases prove that these approaches enhance credibility.