大型武器装备的全寿命周期费用分析

简述了装备全寿命周期费用(LCC)的内涵,比较了美、中武器装备LCC管理过程,阐述了装备效能-费用分析方法、LCC分析的关键问题。     

美国国防部武器系统采办的费用控制

简要介绍了美国国防部实行的DTC(定费用设计)、VE(价值工程)和LCC(全寿命费用)的主要内容和特点,对三者之间的关系进行了研究.笔者认为;在我国军品研制领域,在费用控制方面,应以DTC工作为主体,以VE和LCC工作为手段,使降低费用的上作与设计结合成一个整体.笔者还对通用的价值公式提出了看法.     

航空装备研制中的限成本设计

为了有效控制航空装备研制成本,采用限价设计理念,即美国提出的定费用设计管理方法,并结合国内航空装备研制的特点,研究了限成本设计方法,分析了限成本设计和全寿命周期费用管理的关系,对比了两者优缺点。限成本设计是全寿命周期费用管理的核心部分,决定着全寿命周期费用管理的决策和措施。限成本设计对控制研制成本、提高航空装备产品研发经济性意识具有重要意义。     

武器装备费用确定方法及效费比分析探讨

分析了武器装备的全寿命周期费用的构成及特点,提出用装各经济寿命分析的方法计算出装备的全寿命费用;分析了效能费用的辩证关系,对效费比计算进行了初步的探讨。     

航空装备全寿命周期费用多路径管控策略研究

航空装备作为高新技术复杂产品,其经济性设计越来越受到重视。在满足用户需求的前提下,如何控制并尽可能降低全寿命周期费用是航空装备研究的重点。通过对全寿命周期费用管控理论和方法的研究,总结以往航空装备研制中经济性工作的经验和教训,结合我国军工产品经费管理的特点,从思想观念、管理和技术等方面入手,提出一套在设计阶段适合我国航空装备全寿命周期费用多路径管控的策略,并在某型飞机研制中试点应用。结果表明:某型飞机研制费用管控效果较好,验证了该策略的合理性和有效性。     

基于FMECA的测试性验证分析

随着装备元件的集成度越来越高,对装备测试性的要求越来越高。良好的测试性设计可以有效地提高产品维修性,降低全寿命周期费用。在对通用处理单元进行故障模式、影响和致命度分析(FMECA)的基础上,建立了产品的测试性模型,进行了测试性验证试验,并对验证结果进行分析。     

支持无人机设计的全寿命周期成本建模技术研究

在无人机设计阶段对相关成本进行分析评估，引入按费用设计理念，对于控制无人机装备指标参数与复杂程度、鉴别高费用设计、修正设计进程、提高标准化程度，进而降低全寿命周期费用，实现技术与经济的最佳匹配，达到最优效费比，将起到极其重要的作用。本文分析了一种无人机全寿命周期成本估算框架，研究了无人机全寿命周期成本体系架构，提出了无人机飞机平台全寿命周期成本估算模型，将该模型在某型无人机上进行验证，可以用于无人机研制过程中的设计方案权衡分析和基于成本的设计优化。     

自然环境对航空装备的影响及改善措施

对自然环境尤其是东南沿海气候对航空装备的影响进行了分析，指出空气温度、湿度和盐雾是影响装备正常工作的主要因素，导致装备零部件老化、失效和高故障率。针对南方某机场在飞机维护工作中的探索，总结实践经验，提出了为改进和提高现有航空装备的环境适应性应采取的管理办法和技术措施，为我军布署在东南沿海地区的航空装备的使用维护提供了参考，为提高航空装备战备完好性、降低全寿命周期费用有重要意义。     

机内测试虚警分析和控制

现代飞行器广泛采用机内测试(Built-intest,BIT)技术,以便对其内部故障进行自动检测、诊断和隔离,但是常规BIT面临诊断能力不足和诊断模糊性等问题,导致BIT虚警率高,难以有效发挥其应有的作用.本文论述了BIT虚警的基本理论、虚警的危害及现状,并从BIT虚警产生的原因分析入手,提出了解决虚警问题的一些方法和措施.     

航空装备修理模式对修理成本的影响

目前,我军航空装备修理费用已占到购置费用的15%,航空装备修理成本已经成为全寿命周期成本的重要组成部分。而究其根本,航空装备修理模式是影响修理成本的关键所在,本文将从国外军机、民航飞机、国内军机三个角度出发,研究航空装备修理模式对修理成本的影响,并提出控制军机修理成本的对策建议。     

Role of BIT in support system maintenance and availability

The role of built in test (BIT) in electronic systems has grown in prominence with the advances in system complexity and concern over maintenance lifecycle costs of large systems. In an environment where standards drive system designs (and provide an avenue for focused advancement in technology), standards for BIT are very much in an evolutionary state. The reasons for advancing the effectiveness of BIT include reduced support overhead, greater, confidence in operation, and increased system availability. The cost of supporting military electronic systems (avionics, communications, and weapons systems) has driven much of the development in BIT technology. But what about the systems that support these end items that contain test and measurement instrumentation - such as automatic test equipment (ATE), simulators and avionics development suites? There has also been a beneficial effect on the maintenance and availability of these systems due to the infusion of BIT into their component assemblies. But the effect has been much more sporadic and fragmented. This paper looks at the state of BIT in test and measurement instruments, explain its affect on system readiness, and present ideas on how to improve BIT technologies and standards. This will not provide definitive answers to BIT development questions, since the factors that affect it are specific to the instrument itself. The topics covered in this paper are: definitions of built-in test, instrument BIT history, importance of BIT fault coverage and isolation in support systems, overview of BIT development process issues that limit the effectiveness of BIT Standards related to instrument BIT, making BIT more effective in support system maintenance and availability and conclusions.     

Test results judgment method based on BIT faults

Built-in-test(BIT) is responsible for equipment fault detection, so the test data correctness directly influences diagnosis results. Equipment suffers all kinds of environment stresses, such as temperature, vibration, and electromagnetic stress. As embedded testing facility, BIT also suffers from these stresses and the interferences/faults are caused, so that the test course is influenced,resulting in incredible results. Therefore it is necessary to monitor test data and judge test failures.Stress monitor and BIT self-diagnosis would redound to BIT reliability, but the existing antijamming researches are mainly safeguard design and signal process. This paper focuses on test results monitor and BIT equipment(BITE) failure judge, and a series of improved approaches is proposed. Firstly the stress influences on components are illustrated and the effects on the diagnosis results are summarized. Secondly a composite BIT program is proposed with information integration, and a stress monitor program is given. Thirdly, based on the detailed analysis of system faults and forms of BIT results, the test sequence control method is proposed. It assists BITE failure judge and reduces error probability. Finally the validation cases prove that these approaches enhance credibility.     

基于时间应力分析的机内测试系统综合降虚警技术

 虚警率高是困扰机内测试（BIT）系统得到广泛应用的主要原因。针对该问题,从机电系统所承受时间应力的角度构建了机内测试系统综合降低虚警技术的总体模型。首先采用双支持向量机（SVM）的方法将实时应力信息与机内测试诊断结果相互关联。在此基础上,提出了基于核主元模糊聚类的虚警识别方法将机电系统多源信息进行综合分析,并通过优化决策实现多级降低机内测试系统虚警的目的。最后,针对某型直升机航空地平仪的机内测试系统进行了试验验证与分析。     

飞行控制计算机模拟接口BIT电路设计及仿真

随着航空电子设备维修性要求的提高以及设备本身要求具备检测隔离故障的能力以缩短维修时间,机内测试(BIT)在测试领域研究中将越来越重要。功能电路BIT系统是航空电子设备整机BIT系统的重要组成部分,因此从解决实际问题出发,针对飞行控制计算机中的模拟输入和输出接口电路,提出了几种BIT的设计方法,并使用Multisim软件对所设计的BIT监测电路进行仿真,仿真结果表明,所设计的BIT电路是可靠及有效的。     

BIT综合表示模型研究

 在分析机内测试(BIT)主要设计要素组成的基础上,提出了BIT综合表示模型。建立了BIT综合表示模型的数学定义,包括BIT单元模型、BIT层次关系集合、BIT数据传送方式集合、BIT执行次序集合和BIT综合表示模型。在数学定义的基础上,进一步建立了BIT综合表示的框图模型和表格模型,这两种模型可以直接用于工程分析。最后,以某辅助导航系统为案例,进行了BIT综合表示模型的应用,给出了框图模型结果和表格模型结果,验证了该模型的可用性和有效性。     

Smart BIT: a plan for intelligent built-in test

A major factor influencing the readiness of today's highly electronics-driven weapons systems is the amount of time spent maintaining them. The attainment of a better understanding of the causes for intermittent and other ill-defined failure modes and development of a greater appreciation for the effect of both external and internal environmental factors on the fault behavior of electronic systems will help to improve the BIT (built-in test) performance. Smart BIT is the name applied to a program of research and development sponsored by Rome Air Development Center (RADC) to investigate, develop, and apply artificial-intelligence (AI) techniques to effect BIT improvement. An overview of that program, its contents and purposes is provided. Deficiencies in current BIT implementations and potential benefits of the Smart BIT program are presented. Components of this approach are discussed and supporting technology areas highlighted. The current plan for implementing this approach is given along with a scenario describing its potential form     

Evaluation of built-in test

Built-in test (BIT) provides fault finding as a means to aid in system assembly, test, and maintenance. An investigation to evaluate BIT of a particular electronics board used in the in-flight entertainment system for Boeing 777s is described. We found BIT proved useful when failure occurrences were uniquely associated with the operating environment, situations which can result in no-fault found, or could-not duplicate (CND) failures upon test. We also observed cases where the BIT failed to observe failures, and in some cases pointed to the wrong cause of failure. These and other advantages and disadvantages of BIT implementation are discussed     

机载嵌入式计算机通用化BIT架构设计技术

设计开发了一种通用化BIT软件架构技术,可应用于机载嵌入式计算机.将BIT软件按照功能分为硬件驱动层、测试算法层、测试配置及控制层、应用接口层等,可极大程度实现不同硬件环境、操作系统环境下,BIT软件的可移植性,还定义了一种操作系统启动前实现硬件BIT检测的方法,可有效提高内存、CPU等硬件资源的故障检测率.     

航空电子设备机内自检的设计

介绍了机内自检设计的一般原则;给出了电子设备机内自检的具体设计方案;提出了设计中减少虚警的具体办法。