Generation and classification of PWM DC-to-DC converters

A method is presented by which generation and classification of pulsewidth-modulated (PWM) DC-to-DC converters can be effected. Fundamental blocks known as converter cells can be used to generate a plethora of converters leading to a number of useful new converter topologies. A classification of basic converters is proposed in terms of converter-cell generated families     

Unified approach to developing single-stage power converters

A unified approach to developing single-stage power converters which can fulfil multiple functions is presented. Four synchronous switches corresponding to the four common node types of two active switches are introduced. The approach is then to replace the active switches in multistage converters (in cascade or cascode connection) with one or several of the synchronous switches and their degenerated versions to form a single-stage converter. Illustrations of using these switches to develop single-stage converters are presented. These are started with the development of the well-known single-stage switch-mode converters (SMCs), buck-boost, Cuk, sepic, and Zeta (also named dual sepic), from the basic converters, buck and boost. Then, synthesis and applications of other single-stage converters are addressed. Due to increased component stresses, the developed single-stage converters are primarily suitable for applications with moderate power levels     

An efficient active ripple filter for use in DC-DC conversion

When low ripple is required from a switched mode dc-dc converter, dissipative active filters offer an alternative to passive LC and coupled inductor filters. Analytical and experimental results are presented for a simple active ripple filter. The filter employs a pair of current transformers as sensors for feedforward and feedback control and two metal-oxide-semiconductor field-effect transistors (MOSFETs) as cancellation current drivers. Measurements demonstrate good ripple attenuation up to 5 MHz, more than 70 dB being obtained at 100 kHz, the switching frequency of a test converter. The overall efficiency was measured as 95%, with room for further improvement. The filter is suitable for input and output smoothing in dc-dc converters for aerospace and other critical applications     

高速A/D变换器的电路设计

本文介绍了用常见的中、小规模集成电路设计成高速 A/D 变换器。同时又利用了它的并行传输数字量的速度大大于它本身变换速度的特点,设计了两路在时序上采用相差半个周期来对输入模拟信号交替采样,使 A/D 变换器变换速度达到1MHz 以上。线路实验证明该设计是正确的,实验结果是理想的。并有广泛的使用价值。     

Zero dynamics-based design of damping networks for switching converters

A new design technique of the input filter damping network for dc-to-dc switching converters of buck type is presented. This technique is derived by means of zero dynamics analysis of the switching converter and yields equivalent results to those obtained using the classical approach based on minimizing the filter output impedance. The new method can be applied in converters of buck type with two inductors, boost with two inductors and dual SEPIC. Simulation and experimental results corresponding to a boost converter with two inductors illustrate the procedure.     

Optimal topologies of resonant DC/DC converters

Generalized and optimal topologies of zero-voltage-switching and zero-current-switching resonant DC/DC power converters are presented. It is shown that many equivalent topologies of the converters can be derived from each of the generalized topologies. The generalized topologies of the converters show clearly which of the parasitic capacitances and inductances can be absorbed into the LC resonant circuit. Utilizing this fact, optimal topologies that are the most suitable for high-frequency operation are derived. In the optimal topologies, the greatest possible number of parasitic reactances is included harmlessly in the resonant circuit. Optimum layout and component selection guidelines for the converters are given. High-order resonant converters are also developed     

Planck satellite 70 GHz receiver noise tests

The LFI (Low Frequency Instruments) receivers in the coming Planck satellite are of continuous comparison type and use low noise amplifiers based on high electron mobility transistors manufactured from indium phosphide substrate (INP-HEMT-MMIC-LNAs). This article describes the 1/f-noise tests and the associated test system for the 70 GHz demonstrator receiver, which can either use single or dual channel phase switcher methods. The 1/f knee frequency is shown to depend on the calculation method of the r-value. A minimum 1/f knee frequency around 10 mHz has been achieved with full two channel foxtrot and individually adopted r-values for each phase states while a straightforward single phase technology cannot go below 40 mHz     

A maximum power transfer battery charger for electric vehicles

A battery charger is described that uses an on-line microcontroller to maximize its output power. This is done by always operating at either the maximum allowable input current or the thermal limit imposed by the charger itself. In this case the thermal limit is determined by the junction temperatures of the two main insulated gate bipolar transistors (IGBTs). Since direct measurement of these temperatures is impractical, they must be calculated by a computer algorithm that uses various on-line measurements. Experimental results for an 8 kW charger indicate a reduction in the bulk charging time of about 26% when used with a set of NiFe batteries.     

Improved ZCS-PWM commutation cell for IGBTs application

An improved zero-current-switching pulsewidth-modulated (ZCS-PWM) commutation cell is presented, which is suitable for high-power applications using insulated gate bipolar transistors (IGBTs) as the power switches. It provides ZCS operation for active switches and zero-voltage-switching (ZVS) operation for passive switches. Besides operating at constant frequency and reducing commutation losses, the proposed ZCS-PWM switch cell has no additional current stress and conduction loss in the main switch. To demonstrate the feasibility of the proposed ZCS-PWM commutation cell, it was applied to a boost converter. Operating principle, theoretical analysis, design guidelines, and a design example are described and verified by experiment results obtained from a prototype rated 1 kW and operating at 40 kHz. The PWM switch model and state-space averaging approach is also used to estimate and examine the steady-state and dynamic character of ZCS-PWM boost converter system. Finally, the application of the proposed soft-switching technique in the dc-dc nonisolated converters is presented.     

Single-stage ZVS PWM full-bridge converter

A new soft-switched ac-dc single-stage pulse width modulation (PWM) full-bridge converter is proposed. The converter operates with zero-voltage switching (ZVS), fixed switching frequency, and with a continuous input current that is sinusoidal and in phase with the input voltage. This is in contrast with other ac-dc single-stage PWM full-bridge converters that are either resonant converters operating with variable switching frequency control and high conduction losses, converters whose switches cannot operate with ZVS, or converters that cannot perform power factor correction (PFC) unless the input current is discontinuous. All converter switches operate with soft-switching due to a simple auxiliary circuit that is used for only a small fraction of the switching cycle. The operation of the converter is explained and analyzed, guidelines for the design of the converter are given, and its feasibility is shown with results obtained from an experimental prototype.     

Simplified analysis of PWM converters using model of PWM switch.Continuous conduction mode

A circuit-oriented approach to the analysis of pulsewidth modulation (PWM) converters is presented. This method relies on the identification of a three-terminal nonlinear device, called the PWM switch, which consists of only the active and passive switches in a PWM converter. Once the invariant properties of the PWM switch are determined, its average equivalent circuit model can be derived. This model is versatile enough to easily account for storage-time modulation of bipolar junction transistor(s) (BJTs); the DC- and small-signal characteristics of a large class of PWM converters can then be contained by a simply replacing the PWM switch with its equivalent circuit model. The methodology is very similar to linear amplifier circuit analysis, whereby the transistor is replaced by its equivalent circuit model     

Effect of FET output capacitance on ZVS of resonant converters

The analysis of resonant converters including the capacitance of the switches is presented. New dc characteristics are obtained for the series, parallel, and series-parallel resonant converters (SPRC). The operating regions where the converters operate with zero-voltage switching (ZVS) are determined as a function of the switch capacitance. The more pronounced effect can be seen in the series resonant converter (SRC), while the parallel resonant converter (PRC) is the most insensitive. The results of the analysis have been verified on an experimental prototype     

A digital quadrature demodulation system

Existing digital quadrature demodulation techniques sample the input at either 2B Hz or 4B Hz, select the even samples as the in-phase (I), and interpolate the odd samples to give the quadrature (Q), output. The signal bandwidth is B. We propose a demodulation system to produce I and Q samples at arbitrary sampling rate greater than 2B Hz. The system eliminates the IF downconversion step with a special sampling scheme. The even samples correspond to the I component, while the Q components are the filtered output. The filter can be a lowpass or least squares (LS) filter. The lowpass filter design is based on trade-offs between the filter length and the degree of oversampling. It produces similar results as previous work when the sampling rate is 2B Hz or 4B Hz. Unlike existing methods which assume the input is white, a LS filter, on the other hand, can make use of input signal characteristics to achieve a better result. The higher the correlation in the input the larger the improvement. The cost for LS filtering is a coefficient update step if the input is time varying. A scheme to cancel dc offset from analog to digital (A/D) converters is also given     

Synthesis and analysis of inductor-isolated switched-mode converter

A procedure is developed for the synthesis and analysis of complete classes of inductor-isolated PWM (pulse width-modulated) converters. The procedure is useful in the identification of converters in which the isolation inductors can be integrated with the rest of the inductors on the same magnetic structures. The information obtained from the procedure is useful in the selection of the converter most suitable for a given application and in the design of this converter with minimum component stresses, high power density, and low cost     

Alternate forms of the PWM switch models

Vorperian's pulsewidth modulation (PWM) switch model consists of a PWM transformer and a nonlinear resistor. The recognition that any of the three transformer terminals can serve as the common terminal leads to two alternate PWM transformer models and the corresponding two alternate PWM switch models. For a given PWM dc-dc converter, one of the three PWM switch models is more “natural” for graphic-oriented analysis/design, e.g., it allows the idealized converter to be analyzed by inspection. Furthermore, all three PWM transformers may be used to graphically manipulate the converter circuit to a form that can be analyzed by inspection. The alternate forms of the PWM transformers and the PWM switch models are effective as graphic-oriented teaching and learning tools for PWM converters. This is demonstrated using examples based on the boost converter and the Cuk converter     

Robust controller design for a series resonant converter

Because of their reduced switching losses, allowing a higher operating frequency, dc-to-dc resonant converters have been used extensively in the design of smaller size and lighter weight power supplies. The steady state and dynamic behavior of both the conventional series and parallel resonant converters have been thoroughly analyzed and small-signal models around given nominal operating points have been obtained. These models have been used in the past to design controllers that attempted to keep the output voltage constant in the presence of input perturbations. However, these controllers did not take into account either load or components variations, and this could lead to instability in the face of component or load changes. Moreover, prediction of the frequency range for stability was done a posteriori, either experimentally or by a trial and error approach In this paper we use μ-synthesis to design a robust controller for a series resonant converter (SRC). In addition to robust stability the design objectives include rejection of disturbances at the converter input while keeping the control input and the settling time within values compatible with a practical implementation     

General rules for signal flow graph modeling and analysis of dc-dc converters

Signal flow graph (SFG) nonlinear modeling approach is well known for modeling dc-dc converters. However, all possible SFGs of a given dc-dc converter system will not yield the generalized graph. A systematic procedure and guidelines for developing unified flow graph models of the dc-dc boost converters, from which complete behavior can be determined is presented. Usefulness of the proposed method is demonstrated through examples. As an illustration a 2-cell cascade boost and interleaved boost converter systems are taken as examples. Derivation of large, small-signal and steady-state models from generalized flow graph is also demonstrated. Large-signal model is developed and programmed in TUTSIM simulator. Large-signal, responses against supply and load disturbances are obtained. Experimental observations are provided to validate the proposed algorithm.     

Table-Aided Design of the Energy-Storage Reactor in DC-to-DC Converters

A new procedure for the selection of magnetic cores for use in energy-storage dc-to-dc power converters that eliminates the need for an automated computer search algorithm and stored data file is presented. The converter configurations included in the procedure are the three commonly encountered single-winding converters for voltage stepup, for current stepup and voltage stepup/current stepup, and for the two-winding converter for voltage stepup/current stepup. For each converter configuration, three types of controllers are considered: constant-frequency, constant on-time, and constant off-time. Using concepts developed from analyses of these converters by considering the transfer of energy by means of an energystorage inductor or transformer, a special table of parameters calculated from magnetic core data is constructed, which leads to a considerably simplified design procedure.     

Inherent Overload Protection for the Series Resonant Converter

The overload characteristics of the full bridge series resonant power converter are considered. This includes analyses of the two most common control methods presently in use. The first of these uses a current zero crossing detector to synchronize the control signals and is referred to as the ? controller. The second is driven by a voltage controlled oscillator and is referred to as the ? controller. It is shown that the ? controller has certain reliability advantages in that it can be designed with inherent short circuit protection. Experimental results are included for an 86 kHz converter using power metal-oxide-semiconductor field-effect transistors (MOSFETs).     

Current distribution control for parallel connected converters. I

For pt.II, see ibid., vol.28, no.3, p.841-851 (1992). A master-slave control scheme for a uniform current distribution among converter modules in a parallel connected system is presented. In this technique, inner current loops are introduced to the system to achieve output current equalization. The current distribution error is used as a criterion for judging system performance. Using this control scheme, the current distribution error can be reduced greatly even with nonidentical converters in the system. To optimize system efficiency and facilitate the fault-tolerant algorithm realization, this technique is refined so that only the necessary number of converters are activated for different load conditions