Uniform Sampling Analysis of a Hybrid Phase-Locked Loop with a Sample-and-Hold Phase Detector

Phase-locked-loop (PLL) bit synchronizers often employ integrate-and-dump type phase detectors that provide phase error information only at discrete points in time. Usually these phase detectors are followed by sample-and-hold circuits to produce a stairstep error voltage as the input to a standard analog circuit loop filter. When the loop is configured in this manner, it is referred to as a hybrid PLL. Sampled-data analysis methods (Z transforms) are used to determine the stability and transient response of this loop.     

Graphical Analysis of a Digital Phase-Locked Loop

Under the assumption of negligible quantization error effect and no noise, a nonuniform sampling first-order digital phase-locked loop (DPLL) is analyzed by a graphical method which displays limit cycles and the cycle slipping phenomenon. The analysis suggests an upper bound to the model gain and, consequently, to the pull-in range. Moreover, this method enables one to obtain a closed-form expression of the acquisition time, accurate enough for the cases of practical interest.     

Gated Phase-Locked Loop Study

The objectives of this paper are threefold. The first is to obtain a sampled data model of a gated phase-locked loop. Data from measurements made on an actual loop constructed in the laboratory are included, and the good agreement between measured and calculated results serves as a verification of the model. Second, with the aid of the model, some of the basic operating properties of the system will be presented. Third, comparisons will be made between gated and continuous loop operation.     

Noise Performance of a Gated Phase-Locked Loop

The objectives of this paper are two. The first is to show that a gated phase-locked loop (GPLL) is a tracking device whose operation approximates that of a maximum likelihood estimator of the phase of a pulsed sinusoid imbedded in noise. The second is to determine the behavior of theb loop in the presence of noise. It is found that the loop performance is equivalent to that of a continuous phase-locked loop driven by the same noise, plus a continuous sinusoid which has the same power as the pulsed sinusoid at the input of the GPLL.     

Dynamics of the Phase-Locked Loop without a Limiter

The general (nth order) phase-locked loop is analyzed, of which the amplitude is not constant. The input carrier signal is amplitude-modulated by wide-band stationary Gaussian noise, and the signal, superposed with the additive white stationary Gaussian noise, enters the nonlimited phase-locked loop. Under the above assumptions the loop can be shown to constitute an n-dimensional vector Markov process, so that the process satisfies the n-dimensional Fokker-Plank equation. The probability density function depends on the effective loop signal-to-noise ratio and the effective modulation power.     

Pull-In Performance of a Piecewise Linear Phase-Locked Loop

This is part of a study concerned with the analysis of phase-locked loops (PLL's). The broad objective throughout this work is to improve upon our general understanding in this important area. More particularly, ly, we are seeking quantitative results indicative of the pull-in behavior of PLL's. In the present paper, we point out some results in foreign publications and focus attention on a paper by Kapranov [1] which is devoted to the study of the pull-in frequency of second-order PLL's with a symmetric phase comparator. We apply the same approach and present results, in closed form, in the more general case where the phase comparator possesses an asymmetric triangular characteristic. Special cases of this phase comparator are the sawtooth and symmetric triangular comparators. It can also be viewed as an approximation to the Tanlock phase comparator. The RC filter case is treated.     

Phase-Locked Loop Behavior near Threshold

The phase-locked loop behavior is analyzed following the quasilinearization Booton's method. When the loop is locked on an unmodulated input signal with a static phase error, the phase detector nonlinearity produces an interaction between the static phase error and the voltage-controlled-oscillator (VCO) noise phase fluctuations. Formulas allowing one to compute the static phase error increase and the VCO phase variance increase are derived. When the input signal is phase modulated, there is an interaction between the static phase error, the VCO noise phase fluctuations, and the input signal phase modulation. Formulas are obtained that allow one to compute the loop loss of performances (static phase error increase and VCO phase variance increase) and the coherent phase demodulator output signal-to-noise ratio decrease. Finally, a slight modification to Booton's procedure is proposed, leading to results in better agreement with experimental data.     

Optimum Acquisition of the Idling First-Order Phase-Locked Loop

Acquisition of the idling first-order phase-locked loop (PLL) is investigated. An analytical solution for the Fokker-Planck equation is found if the noise term is neglected. Furthermore, the modulation signal that optimizes the acquisition is obtained by use of phase-plane techniques and Pontryagin's minimum principle.     

Random Characteristics of the Type II Phase-Locked Loop

The results of a study of the characteristics of the second-order Type II phase-locked loop with a Gaussian noise input, and obtained by digital computer simulation, are presented. The digital simulation is described and the random state variables are defined such that their characteristics can be interpreted in terms of existing phase portraits of autonomous phase-locked loops. The statistics associated with the state variables, which are phase error and a measure of frequency error, and those associated with the number of cycles skipped and the mean time to unlock, are given.     

Improved Phase-Locked Loop Performance with Adaptive Phase Comparators

A major problem in phase-locked loop (PLL) design is to meet the requirements of both fast signal acquisition and good synchronous mode performance. This relation is reviewed for different types of phase comparators. As a result a new phase-and-frequency comparator is proposed. This comparator is based on an up-down counter principle and can be considered as an adaptive acquisition control circuit. The analysis of a PLL with the proposed phase comparator is based on an exact calculation method for the pull-in time. It is shown that fast signal acquisition is possible without affecting the filtering properties of the loop. Experimental results are given of the acquisition behavior of a second-order type-2 loop which show a good correspondence with the theoretical analysis.     

Noise Dynamics of the Phase-Locked Loop with Signal Clipping

Employing techniques similar to the averaging methods of Krylov and Bogoliubov, an approximate noise analysis of the phase-locked loop with signal clipping is presented. The validity of the method is demonstrated by comparing the stationary probability density function for the phase error, generated by a system simulation, with the derived theoretical results. The latter portion of the paper discusses the relation of the phase-locked loop to Kalman-Bucy filter theory and presents a demodulator design that illustrates the self-adaptive properties attainable in phase-locked loops with signal clipping.     

基于锁相环的光电振荡器频率稳定化研究

通过构建小数分频锁相环,将一个工作于X波段的OEO(OptoElectronic Oscillator,光电振荡器)与OCXO(Oven-Controlled Crystal Oscillator,恒温晶体振荡器)进行锁相,得到了输出信号相位噪声和长期频率稳定度的提升。从PLL(Phase-Locked Loop,锁相环)环路传输特性出发,理论分析了PLL输出信号环路带宽内相位噪声水平和作用范围。为降低OEO整体的相位噪声,采用SIL(Self-Injection-Locking,自注入锁定)使OEO在10Hz~10kHz频偏处的相位噪声得到20dB以上的抑制。在此基础上将此SIL OEO与一个频率为100 MHz的OCXO锁相,获得了频率为9.95GHz、相位噪声为-55dBc/Hz@10Hz和-124dBc/Hz@10kHz的微波信号输出,其频率的重叠阿伦方差在100s平均时间内达到1.14×10~(-11),证明了提出的方案对提升OEO频率稳定性具有一定的实际意义。     

An Extension of Viterbi's Analysis of the Cycle Slipping in a First-Order Phase-Locked Loop

The phenomenon of cycle slipping in a first-order phase-locked loop is reconsidered and a simple expression for the expected number ? of cycles slipped per second is given in the form of a rapidly converging series. In this way the computation of ? becomes much easier than with previously known formulas. A formula allowing the computation of the expected number of cycles gained or lost per second is also given. These results are obtained by extending a technique used by Viterbi. The outcome of experimental verifications of the theory is also reported.     

S频段小数分频锁相环频率合成器实现与应用

传统的整数分频锁相环频率合成技术无法在单个环路实现高频率、低分辨率和低相噪的目标,小数分频锁相环在提高鉴相频率的同时减小分频计数值,从而降低相位噪声。针对USB统一测控系统的需要,本文提出基于单片小数分频锁相环的微波频率合成方法。实验结果表明,小数分频锁相环频率合成器具备良好的信号输出特性,可以为测控系统提供低成本频率合成方案。     

Identical Steady-State Results for a Kalman Tracker

It is shown that the analytical results presented in [2, 3] for determining the steady state gain and error covariance matrices of the two state Kalman tracker [1] are identical although they appear to be different.     

Effects of Automatic Gain Control on Phase-Locked Loop Behavior in the Presence of Interference

The behavior of a second-order phase-locked loop (PLL) in the presence of an interfering signal has been analyzed by different authors with different results. The discrepancy is attributed to the presence or absence of an automatic gain controlled amplifier preceeding the PLL. Simulation results verify that the presence of the automatic gain controlled amplifier reduces the tendency of the PLL to break lock from the desired signal in favor of the interfering signal     

无人机/载机近距飞行的简化稳定性判据

无人机蜂群密集飞行和无人机空中回收都涉及到无人机/载机在近距干扰流场中的飞行稳定性问题。针对上述应用背景,采用无人机/载机干扰气动导数模型,分析近距飞行的影响因素,采用纵向运动动力学方程,推导出其简化稳定性判据,并采用典型飞行器参数进行初步分析。通过数值仿真分析,结果表明：该简化判据反映了无人机运动稳定性与气动特性、干扰流场特性的关系,可用于相关无人机在干扰流场中飞行稳定性初步分析和设计;干扰流场中的下洗效应可使无人机出现幅值收敛较慢的短周期模态运动,增加了干扰流场中实现稳定可控飞行的难度。     

激光跟踪测量系统

介绍了激光跟踪测量系统的组成、工作原理、测量方法,并就其使用中应注意的问题作了阐述.