Fault-Tolerant Memory System Architecture for Radiation Induced Errors

A fault-tolerant memory (FTM) architecture is presented which can be used to overcome soft memory errors induced by alpha particles, cosmic radiation, or other random sources. The characteristics of the FTM are presented, a mathematical model is developed, and numerical examples are considered to illustrate the effectiveness of the approach. The FTM architecture has been incorporated in the NASA Standard Spacecraft Computer (NSSC-II) which will be employed in a variety of future space payloads and experiments.     

Simplified Solution for a Class of Fading Memory Filters

A fading memory filter is a least squares estimator (LSE) thatapplies an exponentially decaying weight to past measurements.When compared with a standard Kalman filter, its key advantagesare asymptotic stability and reduced sensitivity to modeling errors.This paper derives a simple solution for a class of fading memoryfilters, resulting in a reduction in computational complexity. Steadystate filter solutions are obtained for second-and third-order filtersused in a global positioning system (GPS) receiver for high dynamicvehicles.     

Data path synthesis in digital electronics. I. Memory allocation

A data path consists of memory elements (i.e., registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to hardware allocation for data path synthesis have been proposed in the literature; however, only single-port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. A novel design methodology for data path synthesis using multiport memories is proposed which can be applied to hardware allocation algorithms or to already synthesized data path as a postprocessor to achieve a better design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. Experiments on benchmarks show very promising results     

振动时效对NiTi记忆合金双程记忆应变的影响

研究了振动时效对NiTi形状记忆合金双程记忆效应的影响.结果表明,当预应变较小或较大时,经过振动时效后NiTi合金的双程应变量增加;当预应变适中时,振动时效后NiTi合金的双程应变量减小.这可能是由于振动时效在NiTi合金中产生了微观塑性变形,改变了合金中的双程应力场而导致的.     

氢化环氧树脂体系形状记忆效应的研究

将顺丁烯二酸酐(MA)与不同比例的氢化环氧树脂、聚丙二醇二缩水甘油醚(PPGDGE)共混,经完全固化制备出一种新型的形状记忆氢化环氧树脂体系。利用DMA,DSC、弯曲测试和U型形状记忆测试系统研究了该固化体系的动态力学性能、力学性能和形状记忆性能,结果表明:该固化体系交联点之间存在较长的柔性链段,导致部分结晶现象的出现;固化体系的玻璃化转变温度(Tg)最高达124℃,并且Tg随PPGDGE含量的增加而线性降低;该形状记忆氢化环氧固化体系具有优良的形状记忆性能,经过5次形状记忆测试,变形的试样均能在数分钟内完全恢复到变形前的状态,形变恢复率达100%。     

Feedback Transmission of Binary Data with Automaton Receiver

Feedback transmission of binary data over a discrete-time additive Gaussian white noise channel is considered. The effect of some specific finite memory structure at the receiver is investigated. The whole communication scheme is the discrete analog of the one previously analyzed by Khas'minskii. The resulting average transmission time is increased by only about 20 percent of the theoretical limit in the low signal-to-noise ratio region. Numerical results are also shown.     

Linux 2．6内存保护机制研究

基于Intel i386平台处理器和Linux 2.6内核源代码,从硬件内存保护和虚拟内存保护两个方面分析了最新的Linux内存保护机制,其中硬件内存保护机制包括段式映射阶段的访问控制、页式映射阶段的访问控制以及最新内存保护NX(No eXecute)技术,虚拟内存保护机制包括虚拟区间保护、虚拟区间加锁和Hole技术.最后进一步讨论了增强Linux内存保护的方案.     

高周疲劳损伤的磁记忆二维检测研究

 对40Cr钢缺口试件在三级应力水平下进行了高周疲劳试验和磁记忆二维检测(2-D MMMT),并引入李萨如图分析方法,研究应力集中、疲劳损伤及疲劳应力对二维磁信号的影响规律,分析李萨如图特征值与疲劳损伤程度之间的关系。结果表明:在应力集中部位会出现磁记忆法向分量过零点及切向分量峰值的现象,并且该现象的位置随着疲劳损伤程度的增加产生漂移,逐渐向缺口根部靠拢;可利用磁记忆信号切向分量梯度K曲线异变峰特征来表征构件损伤位置;磁记忆信号切向分量梯度最大值随疲劳损伤程度的增大而增加;磁记忆信号梯度K曲线形成的李萨如图闭合区域面积与疲劳损伤程度有较好的对应关系。梯度最大值可作为反映构件损伤程度的特征量,根据李萨如图面积可以判断构件疲劳损伤状态。     

面向安全的内存管理子系统研究

以开发具有自主知识产权的军用安全OS为背景,基于最新版本Linux内核,分析并设计安全内存管理子系统.依据可信计算机系统评估标准,将安全OS的功能需求依次映射到内存管理子系统,初步提出安全内存管理子系统的四个功能:进程隔离、防止内存信息泄露、内存访问控制,虚拟内存保护;在分析Linux内存管理机制的基础上,采用安全增强法,从安全相关和硬件相关出发分解核心程序,提出安全增强型内存管理子系统的设计方案,并对各部分进行了分析和实现.     

Fe和Nb对TiNi形状记忆合金环双程记忆效应的影响

研究了预变形和热循环对Ti50.8Ni49.2及加入Fe和Nb后合金环的双程记忆应变影响。结果表明:在马氏体状态进行10.4%~13.8%的预变形,TiNi合金环随循环次数增加,双程记忆应变增大,在13.8%预变形和4次循环得到4.15%最大值;加入Fe和Nb后,在10.71%~15.18%的变形范围,合金环的双程记忆应变先增后降,其最大值分别为3.14%和2.56%。在变形量和循环次数相同时,TiNi合金环的记忆应变最高,当变形量和循环次数超过12.50%和2以后,TiNiFe合金环的双程记忆应变快速上升,其双程记忆应变超过TiNiNb合金环的。     

基于FPGA和VHDL的嵌入式存储器控制器设计

主要研究一种新型嵌入式对存储器的控制方法,不同于以往采用专用控制器来进行控制,而是基于可编程逻辑器件(FPGA)的手段来实现对存储器的控制.可以解决传统方法低灵活性、不可擦写的瓶颈问题.采用VHDL语言实现控制逻辑,由FPGA向存储器发送读写信号,实现对存储器的读写操作.同时,在Xilinx开发环境进行综合,编写测试码进行仿真,通过仿真结果表明方法实现存储器正常工作所需要的读写时序,证明其正确性.     

High-efficiency Loran-C interference identification by synchronous sampling

A new technique is proposed for estimating the frequencies within carrier-wave interference (CWI) affecting Loran-C receivers. Its novelty lies in that interference samples are taken synchronously with the Loran-C pulses and ensemble-averaged in the time domain prior to conventional spectrum analysis. Each interferer is thus automatically weighted according to its effect on the phase tracking operation of the receiver. The new method substantially increases the efficiency with which the most insidious interferers may be pinpointed. It requires little additional computational power or memory in the receiver.     

ATC模拟系统中存贮系统的容错技术

ATC 模拟系统是一个比较复杂的,实时性很强的控制系统,要求整个系统的可靠性很高。而对于一个系统来讲,其中央存贮系统是保证整个系统正常工作的关键部件之一。在我们引进的系统中,它的容错技术在设计上有其独到之处。本文就其存贮系统的结构、容错技术及支持电路这三部分予以说明和论述,仅供同行参考。     

空间静态配置算法的研究与应用

对嵌入式操作系统设计中的存储空间静态配置进行了分析。在简要介绍空间静态配置基本原理的基础上,重点阐述了静态空间划分的具体实现方法以及空间静态配置系统的设计与组成,并对静态配置算法和动态配置算法进行了对比分析,最后介绍静态空间配置算法的具体应用实例。     

航空铁磁材料磁记忆检测新方法

 为提高现有磁记忆检测方法的可靠性,充分考虑各向磁记忆信号分量特征,提出法向和切向相结合的磁记忆检测新方法,对航空铁磁材料18CrNi4A试件在不同拉伸载荷下同时采集法向和切向两个方向上的磁记忆信号,并对信号进行小波包滤波处理后取李萨如图,用图中封闭区域出现的位置判断应力集中部位,用封闭区域面积的大小判断应力集中程度,研究磁记忆信号法向分量和切向分量联合检测材料的应力状态。结果表明:对该材料试件磁记忆信号法向分量和切向分量进行小波包降噪方法切实可行,处于应力集中试件的磁记忆信号反映在李萨如图上会出现封闭区域,并且随着应力集中程度的增大,李萨如图上封闭区域的面积有增大趋势,材料出现明显屈服后,面积增大得更加明显。该方法具有一定的工程实际应用价值。     

一种改进的变记忆长度辨识算法

本文基于多分辨分析方法 ,提出了一种改进的变记忆长度的小波变换多分辨分析方法 ,该方法将辨识的数据分解到不同频段 ,然后针对各不同频段采用不同的记忆长度进行辨识 ,通过对某航空涡轮起动机系统辨识的实例 ,表明该方法可以有效地提高系统辨识的精度。     

High Hardware Utilization and Low Memory Block Requirement Decoding of QC-LDPC Codes

This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check (QC-LDPC) codes, which not only achieves high hardware utility efficiency (HUE), but also brings about great memory block reduction without any performance degradation. The main idea is to split the check matrix into several row blocks, then to perform the improved message passing computations sequentially block by block. As the decoding algorithm improves, the sequential tie between the two-phase computations is broken, so that the two-phase computations can be overlapped which bring in high HUE. Two overlapping schemes are also presented, each of which suits a different situation. In addition, an efficient memory arrangement scheme is proposed to reduce the great memory block requirement of the LDPC decoder. As an example, for the 0.4 rate LDPC code selected from Chinese Digital TV Terrestrial Broadcasting (DTTB), our decoding saves over 80% memory blocks compared with the conventional decoding, and the decoder achieves 0.97 HUE. Finally, the 0.4 rate LDPC decoder is implemented on an FPGA device EP2S30 (speed grade -5). Using 8 row processing units, the decoder can achieve a maximum net throughput of 28.5 Mbps at 20 iterations.     

NiTiHf高温形状记忆合金研究进展

介绍了NiTiHf高温形状记忆合金的研究状况 ,重点评述了NiTiHf合金的设计以及Hf的添加和热处理对合金的相变、力学行为和形状记忆效应的影响 ,并对它们所对应的微观机制作了一定的分析     

基于FPGA的数字存储示波器

基于FPGA的数字存储示波器,以可编程逻辑器件ACEX1K30TC144-3和89c51单片机为核心,由通道输入调整、数据采集、数据处理、波形显示和操作面板等功能模块组成.系统中的数据采集及数据处理模块,采用了FPGA内制的RAM IP核,使系统的工作频率基本不受外围器件影响,经maxplusⅡ延时分析,其内核频率可以达到40 MHz以上,这对于数据处理速度和实时性要求比较高的应用领域具有重要的意义.