Role of BIT in support system maintenance and availability

The role of built in test (BIT) in electronic systems has grown in prominence with the advances in system complexity and concern over maintenance lifecycle costs of large systems. In an environment where standards drive system designs (and provide an avenue for focused advancement in technology), standards for BIT are very much in an evolutionary state. The reasons for advancing the effectiveness of BIT include reduced support overhead, greater, confidence in operation, and increased system availability. The cost of supporting military electronic systems (avionics, communications, and weapons systems) has driven much of the development in BIT technology. But what about the systems that support these end items that contain test and measurement instrumentation - such as automatic test equipment (ATE), simulators and avionics development suites? There has also been a beneficial effect on the maintenance and availability of these systems due to the infusion of BIT into their component assemblies. But the effect has been much more sporadic and fragmented. This paper looks at the state of BIT in test and measurement instruments, explain its affect on system readiness, and present ideas on how to improve BIT technologies and standards. This will not provide definitive answers to BIT development questions, since the factors that affect it are specific to the instrument itself. The topics covered in this paper are: definitions of built-in test, instrument BIT history, importance of BIT fault coverage and isolation in support systems, overview of BIT development process issues that limit the effectiveness of BIT Standards related to instrument BIT, making BIT more effective in support system maintenance and availability and conclusions.     

飞行控制计算机模拟接口BIT电路设计及仿真

随着航空电子设备维修性要求的提高以及设备本身要求具备检测隔离故障的能力以缩短维修时间,机内测试(BIT)在测试领域研究中将越来越重要。功能电路BIT系统是航空电子设备整机BIT系统的重要组成部分,因此从解决实际问题出发,针对飞行控制计算机中的模拟输入和输出接口电路,提出了几种BIT的设计方法,并使用Multisim软件对所设计的BIT监测电路进行仿真,仿真结果表明,所设计的BIT电路是可靠及有效的。     

Implementing reusable, instrument independent test programs in thefactory

Development of computer programs that control test sequences on Automatic Test Equipment (ATE) is costly and time consuming. Test Programs are usually written by specifying the instruments to be used in the ATE and the sequence of the setup and measurement parameters for these instruments. Reuse of test program software on other ATE is usually not possible without rewriting, revalidating and re-releasing the programs. This paper describes an implementation of a test program software development system and a standard of software runtime architecture used in our factories. The object-oriented development environment and its associated class libraries allow test programs to be written without knowledge of the ATE on which they will be run. Two main principles guided the design: the software architecture was based on recognized formal and industry standards; and our implementation used commercial off-the-shelf software products when possible. Emerging standards such as the IEEE-1226 (ABBET) as well as defacto industry standards including VXI Plug and Play have made our implementation possible. The current draft of the ABBET and P&P standards do not promote this instrument independence, but it is hoped that this will be added as the standards mature. Three immediate benefits are: cost savings that result from reusing validated test programs; cycle time reductions that result from concurrently developing test program software and ATE; and software defect reductions that result from using proven software     

Development of a TPS reuse library using COTS tools

In the past, functional test requirements (FTR) or test requirement documents (TRD) and test program sets (TPS) were standalone items developed by individual engineers. In some cases, one engineer would write the FTR/TRD and another would develop the TPS. Commercial ATLAS FTRs are prepared in ARINC 616 and 626 ATLAS. Military TRDs are written in IEEE ATLAS 716 versions. Previous test reuse attempts have not been successful because additional software, like browsers, is required to support these efforts. It was difficult to justify writing new software; for example, browsers to manage the application software. Today, commercial-off-the-shelf (COTS) tools are in place to browse and view information from circuit diagrams to documents to source code. These tools can develop hierarchies to organize the information. These COTS tools are available throughout Boeing on many types of workstations and personal computers on every engineer's desk. This paper discusses how a reusable test library (RTL) is being developed using commercial-off-the-shelf (COTS) tools, such as Mosaic, to address commercial and military test applications. It describes each of the tools and the process to develop TPSs using the reuse library. It defines the metrics and benefits achieved     

机内测试定量要求的现场试验验证方法研究

阐述了机内测试(BIT)定量要求现场试验验证方法的内涵和实施流程。根据置信度水平和功能单元覆盖要求计算BIT故障检测率、故障隔离率和虚警率综合验证的样本量,根据BIT参数的单侧置信限进行合格判断。给出了数据统计判据、分类流程和统一记录表格。通过案例应用说明了该方法的可行性。     

Smart BIT: a plan for intelligent built-in test

A major factor influencing the readiness of today's highly electronics-driven weapons systems is the amount of time spent maintaining them. The attainment of a better understanding of the causes for intermittent and other ill-defined failure modes and development of a greater appreciation for the effect of both external and internal environmental factors on the fault behavior of electronic systems will help to improve the BIT (built-in test) performance. Smart BIT is the name applied to a program of research and development sponsored by Rome Air Development Center (RADC) to investigate, develop, and apply artificial-intelligence (AI) techniques to effect BIT improvement. An overview of that program, its contents and purposes is provided. Deficiencies in current BIT implementations and potential benefits of the Smart BIT program are presented. Components of this approach are discussed and supporting technology areas highlighted. The current plan for implementing this approach is given along with a scenario describing its potential form     

Software architecture for building

Test system developers can benefit greatly from a software architecture that allows for easy interchangeability of instruments in those systems. Using open industry standard software architectures such as Virtual Instrument Software Architecture (VISA), and Interchangeable Virtual Instruments (IVI), developers are able to create systems with interchangeable test instrumentation. This paper describes the VISA and IVI software standards and demonstrates how their use within a broader software architecture, which includes standard development environments and flexible test executive software, facilitates the creation of interchangeable test systems     

Correlation analysis of combined and separated effects of wing deformation and support system in the CAE-AVM study

The Chinese Aeronautical Establishment (CAE) Aerodynamic Validation Model (AVM) is a dual-purpose test geometry dedicated to verify the aerodynamic performance of a conceptual intercontinental jet aircraft and to provide a dataset for CFD software validation. To this end, a scaled model of the AVM was tested in the High-Speed Tunnel (HST) of the German-Dutch Wind-tunnels (DNW) with special test consideration and instrumentation. For complementary analysis of experimental results, specific CAE-AVM geometries are analyzed using a CAE in-house CFD code. The specific geometries consist of a baseline aircraft, an aircraft with a deformed wing shape, and an aircraft with both a deformed wing shape and a representation of the model support system used in the wind tunnel. Detailed analysis of numerical and experimental results is presented; both the combined and individual attributions of wing deformation and support system interference on wing pressure distributions and longitudinal aerodynamic characteristics are summarized.     

An alternative to traditional software rehosting

This paper describes one alternative to rehosting TPS software to newer computer platforms. It describes the solution that Southwest Research Institute (SwRI) used to solve a problem with re-engineering legacy software into a modern object-oriented language. The advantages gained by this method are more advanced instruction to the operator (such as pictures and movies), flexible reporting scheme to diagnose system problems, and ease of software maintenance. This solution uses commercially available products including National Instruments/spl trade/ TestStand/spl trade/ and LabVIEW/spl trade/ and Microsoft/spl reg/ Visual Basic/spl reg/. The system is a four-tiered architecture to drive all test execution. The user interface is written in Visual Basic and allows the user to interact with the test execution when needed. This user interface in turn calls tests that are written in TestStand, and finally the individual tests call driver functions written in LabVIEW. A database serves as a repository for all test results, displays, and test limits. The use of this database allows for easy querying of measurement data to analyze trends in failures that help diagnose specific problems. By using this database, all test limits and test displays are contained in one central location that enables engineers to change these displays and limits on the fly without needing to change or even understand any test code. One other benefit of this data containment is that all Government classified data is separated out of the code and stored as one file, instead of in various locations as it was in the original source code.     

智能检测技术在靶场测控设备中的应用及前景

综合运用先进的GPS授时技术和数字仿真、虚拟仪器结构、可视化编程等计算机软件技术，构建新一代靶场智能型检测系统，解决对野外分散站点上测控设备进行检测、标校、监控和测控网通信联试等技术问题。着重阐述智能化检测技术在靶场的应用及发展趋势，为技术人员开发测试软件提供参考。     

机载嵌入式计算机通用化BIT架构设计技术

设计开发了一种通用化BIT软件架构技术,可应用于机载嵌入式计算机.将BIT软件按照功能分为硬件驱动层、测试算法层、测试配置及控制层、应用接口层等,可极大程度实现不同硬件环境、操作系统环境下,BIT软件的可移植性,还定义了一种操作系统启动前实现硬件BIT检测的方法,可有效提高内存、CPU等硬件资源的故障检测率.     

Analysis tools for the evaluation of maintenance software

Test packages written for built-in test (BIT) and mobile automatic test equipment (ATE) systems for the forward support of electronic and thermal imaging equipment used by the British Army are currently scrutinized and subjected to objective tests by test package evaluation and acceptance teams (TPEATs) before being accepted for field use. This is a time-consuming and costly exercise that can result in the rejection of unsuitable software. The result of such rejection on equipment logistics is for reaching, since the hardware will enter service without adequate maintenance support. In an attempt to address this problem a suite of programs aimed at assisting the verification and validation activities of the TPEAT at every stage of the software life cycle from requirements analysis through to testing and acceptance is being devised. The development of these tools is discussed     

Test results judgment method based on BIT faults

Built-in-test(BIT) is responsible for equipment fault detection, so the test data correctness directly influences diagnosis results. Equipment suffers all kinds of environment stresses, such as temperature, vibration, and electromagnetic stress. As embedded testing facility, BIT also suffers from these stresses and the interferences/faults are caused, so that the test course is influenced,resulting in incredible results. Therefore it is necessary to monitor test data and judge test failures.Stress monitor and BIT self-diagnosis would redound to BIT reliability, but the existing antijamming researches are mainly safeguard design and signal process. This paper focuses on test results monitor and BIT equipment(BITE) failure judge, and a series of improved approaches is proposed. Firstly the stress influences on components are illustrated and the effects on the diagnosis results are summarized. Secondly a composite BIT program is proposed with information integration, and a stress monitor program is given. Thirdly, based on the detailed analysis of system faults and forms of BIT results, the test sequence control method is proposed. It assists BITE failure judge and reduces error probability. Finally the validation cases prove that these approaches enhance credibility.     

基于时间应力分析的机内测试系统综合降虚警技术

 虚警率高是困扰机内测试（BIT）系统得到广泛应用的主要原因。针对该问题,从机电系统所承受时间应力的角度构建了机内测试系统综合降低虚警技术的总体模型。首先采用双支持向量机（SVM）的方法将实时应力信息与机内测试诊断结果相互关联。在此基础上,提出了基于核主元模糊聚类的虚警识别方法将机电系统多源信息进行综合分析,并通过优化决策实现多级降低机内测试系统虚警的目的。最后,针对某型直升机航空地平仪的机内测试系统进行了试验验证与分析。     

The network centric test system

Network topology is an important choice for the test system designer. There are several to choose from and each has benefits. A comparison of topologies is made based on the benefits and drawbacks for various usage situations. Some of the topologies of interest are: placing the instrumentation and the controller on the corporate intranet; using switching hubs for traffic isolation; using a second LAN connection in the test system controller as a private network for instrumentation; placing a router between the intranet and the test system controller; and widely distributing test assets. Test asset visibility to the rest of the network has both security and test integrity implications. Trading off the benefits of ready access and observation (which promotes collaboration) against system visibility needs to be carefully examined. Several use cases will be presented for examination: simply connected user; semi-automated test; fully automated test; and remote collaboration for system problem-solving.     

How Engineers Can Conduct Cost-Benefit Analysis for PHM Systems

Individuals who work in the field of Prognostic and Health Management (PHM) technology have come to understand that PHM can provide the ability to effectively manage the operation, maintenance, and logistic support of individual assets or groups of assets through the availability of regularly updated and detailed health information. Naturally, prospective customers of PHM technology ask: "How will the implementation of PHM benefit my organization?" Typically, the response by individuals in the field is: "Anecdotal evidence indicates that PHM decreases maintenance costs, increases operational availability, and improves safety." This information helps the prospective customer understand the practical benefits of the technology, but that customer stills needs more information to justify their investment in the technology. The customer needs a calculated return on investment (ROI) figure for their particular asset that provides financial assessment of the benefit of the investment. The data, time, and expertise required to conduct a rigorous cost benefit analysis makes the effort seem daunting to the average engineer with little to no fimancial analysis training. The reality is that with a cursory understanding of the asset operation, maintenance, and logistic issues, a useful cost-benefit analysis can be conducted by engineers without business school training. Our purpose herein is to provide a general methodology for conducting a preliminary cost-benefit analysis that calculates an ROI for PHM implementation. We discuss the general types of information needed for the analysis, the quantifying of expected benefits, and the types of supporting data required to validate the benefit assumptions as well as an outline for the costing of PHM technology.     

Flyable fiber-optic radar target generator

Airborne radar relies on Built-in-Test (BIT) for fault detection, fault isolation and system calibration. The capability of BIT is often limited by space, weight, size and cost considerations. Furthermore, the radar does not have a test target that will allow BIT to perform in flight, closed-loop functional test of the complete radar system. This paper describes a fiber-optic based radar test target unit that provides a delayed replica of the transmitted radar signal. The unit will intercept a small amount of radar-transmitted energy, delay it in the fiber, then feed it back into the radar producing a calibrated “echo” at a predetermined radar range. The unit can be installed as part of the airborne radar. The details on the design and testing of a proof-of-concept unit are also given     

Using built-in-test to reduce TPS run times and improve TPSreliability

This paper addresses using information derived from Built-in-Test (BIT) to fault diagnose Units Under Test (UUTs), wherever possible. This philosophic approach to diagnostic testing is not new. It has been studied over the past 20 years under the visor of “Integrated Diagnostics”, but it has yet to be truly implemented in a “real life” military diagnostic test environment. The mindset of Test Program Set design engineering, along with customer and contractor management alike, remains “complete diagnostic testing based upon single catastrophic component failure modes”. If we are to generate cost efficient Test Program Sets (TPSs) under reduced military budget constraints, this will have to change! The test engineer must be encouraged to use methodologies to speed up development time and decrease TPS run times. Using present technology, this is possible now, and as the technology matures, will become a truly viable approach in the future. For the purpose of this paper, the author relies heavily on his extensive US Navy Automatic Test Equipment (ATE) and Test Program Set (TPS) experience, as well as on previous studies performed on using BIT to fault diagnose Unit Under Test failures on US Naval Air weapon systems     

Environmental stress level evaluation approach based on physical model and interval grey association degree

 Associating environmental stresses (ESs) with built-in test (BIT) output is an important means to help diagnose intermittent faults (IFs). Aiming at low efficiency in association of traditional time stress measurement device (TSMD), an association model is built. Thereafter, a novel approach is given to evaluate the integrated environmental stress (IES) level. Firstly, the selection principle and approach of main environmental stresses (MESs) and key characteristic parameters (KCPs) are presented based on fault mode, mechanism, and ESs analysis (FMMEA). Secondly, reference stress events (RSEs) are constructed by dividing IES into three stress levels according to its impact on faults; and then the association model between integrated environmental stress event (IESE) and BIT output is built. Thirdly, an interval grey association approach to evaluate IES level is proposed due to the interval number of IES value. Consequently, the association output can be obtained as well. Finally, a case study is presented to demonstrate the proposed approach. Results show the proposed model and approach are effective and feasible. This approach can be used to guide ESs measure, record, and association. It is well suited for on-line assistant diagnosis of faults, especially IFs.     

基于模糊Petri网的维修保障活动可视化建模与仿真研究

介绍了模糊Petri网矩阵推理算法,并对模糊Petri网中的元素进行了抽象定义,同时,为了仿真实现矩阵推理算法,定义了用于存储模型数据和中间计算结果的动态数组,并给出具体代码建模流程图。最后,作为验证实例,应用飞机前轮更换轮胎对该维修保障活动仿真软件进行验证。结果表明,该软件可对该维修保障活动进行建模,即直观清晰地体现出飞机某环节维修保障活动的进程,同时也可以根据相关参数进行分析,将能为在航空系统产品保障效能评估中找出可靠性、维修性、测试性和保障性设计存在的薄弱环节提供技术支持。